1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _MACTX_PHY_DESC_H_ 20 #define _MACTX_PHY_DESC_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_MACTX_PHY_DESC 4 25 26 #define NUM_OF_QWORDS_MACTX_PHY_DESC 2 27 28 29 struct mactx_phy_desc { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t reserved_0a : 16, 32 bf_type : 2, 33 wait_sifs : 2, 34 dot11b_preamble_type : 1, 35 pkt_type : 4, 36 su_or_mu : 2, 37 mu_type : 1, 38 bandwidth : 3, 39 channel_capture : 1; 40 uint32_t mcs : 4, 41 global_ofdma_mimo_enable : 1, 42 reserved_1a : 1, 43 stbc : 1, 44 dot11ax_su_extended : 1, 45 dot11ax_trigger_frame_embedded : 1, 46 tx_pwr_shared : 8, 47 tx_pwr_unshared : 8, 48 measure_power : 1, 49 tpc_glut_self_cal : 1, 50 back_to_back_transmission_expected : 1, 51 heavy_clip_nss : 3, 52 txbf_per_packet_no_csd_no_walsh : 1; 53 uint32_t ndp : 2, 54 ul_flag : 1, 55 triggered : 1, 56 ap_pkt_bw : 3, 57 ru_position_start : 8, 58 pcu_ppdu_setup_start_reason : 3, 59 tlv_source : 1, 60 reserved_2a : 2, 61 nss : 3, 62 stream_offset : 3, 63 reserved_2b : 2, 64 clpc_enable : 1, 65 mu_ndp : 1, 66 response_expected : 1; 67 uint32_t rx_chain_mask : 8, 68 rx_chain_mask_valid : 1, 69 ant_sel_valid : 1, 70 ant_sel : 1, 71 cp_setting : 2, 72 he_ppdu_subtype : 2, 73 active_channel : 3, 74 generate_phyrx_tx_start_timing : 1, 75 ltf_size : 2, 76 ru_size_updated_v2 : 4, 77 reserved_3c : 1, 78 u_sig_puncture_pattern_encoding : 6; 79 #else 80 uint32_t channel_capture : 1, 81 bandwidth : 3, 82 mu_type : 1, 83 su_or_mu : 2, 84 pkt_type : 4, 85 dot11b_preamble_type : 1, 86 wait_sifs : 2, 87 bf_type : 2, 88 reserved_0a : 16; 89 uint32_t txbf_per_packet_no_csd_no_walsh : 1, 90 heavy_clip_nss : 3, 91 back_to_back_transmission_expected : 1, 92 tpc_glut_self_cal : 1, 93 measure_power : 1, 94 tx_pwr_unshared : 8, 95 tx_pwr_shared : 8, 96 dot11ax_trigger_frame_embedded : 1, 97 dot11ax_su_extended : 1, 98 stbc : 1, 99 reserved_1a : 1, 100 global_ofdma_mimo_enable : 1, 101 mcs : 4; 102 uint32_t response_expected : 1, 103 mu_ndp : 1, 104 clpc_enable : 1, 105 reserved_2b : 2, 106 stream_offset : 3, 107 nss : 3, 108 reserved_2a : 2, 109 tlv_source : 1, 110 pcu_ppdu_setup_start_reason : 3, 111 ru_position_start : 8, 112 ap_pkt_bw : 3, 113 triggered : 1, 114 ul_flag : 1, 115 ndp : 2; 116 uint32_t u_sig_puncture_pattern_encoding : 6, 117 reserved_3c : 1, 118 ru_size_updated_v2 : 4, 119 ltf_size : 2, 120 generate_phyrx_tx_start_timing : 1, 121 active_channel : 3, 122 he_ppdu_subtype : 2, 123 cp_setting : 2, 124 ant_sel : 1, 125 ant_sel_valid : 1, 126 rx_chain_mask_valid : 1, 127 rx_chain_mask : 8; 128 #endif 129 }; 130 131 132 133 134 #define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 135 #define MACTX_PHY_DESC_RESERVED_0A_LSB 0 136 #define MACTX_PHY_DESC_RESERVED_0A_MSB 15 137 #define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff 138 139 140 141 142 #define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 143 #define MACTX_PHY_DESC_BF_TYPE_LSB 16 144 #define MACTX_PHY_DESC_BF_TYPE_MSB 17 145 #define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 146 147 148 149 150 #define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 151 #define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 152 #define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 153 #define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 154 155 156 157 158 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 159 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 160 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 161 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 162 163 164 165 166 #define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 167 #define MACTX_PHY_DESC_PKT_TYPE_LSB 21 168 #define MACTX_PHY_DESC_PKT_TYPE_MSB 24 169 #define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 170 171 172 173 174 #define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 175 #define MACTX_PHY_DESC_SU_OR_MU_LSB 25 176 #define MACTX_PHY_DESC_SU_OR_MU_MSB 26 177 #define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 178 179 180 181 182 #define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 183 #define MACTX_PHY_DESC_MU_TYPE_LSB 27 184 #define MACTX_PHY_DESC_MU_TYPE_MSB 27 185 #define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 186 187 188 189 190 #define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 191 #define MACTX_PHY_DESC_BANDWIDTH_LSB 28 192 #define MACTX_PHY_DESC_BANDWIDTH_MSB 30 193 #define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 194 195 196 197 198 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 199 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 200 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 201 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 202 203 204 205 206 #define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 207 #define MACTX_PHY_DESC_MCS_LSB 32 208 #define MACTX_PHY_DESC_MCS_MSB 35 209 #define MACTX_PHY_DESC_MCS_MASK 0x0000000f00000000 210 211 212 213 214 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 215 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 36 216 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 36 217 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000001000000000 218 219 220 221 222 #define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x0000000000000000 223 #define MACTX_PHY_DESC_RESERVED_1A_LSB 37 224 #define MACTX_PHY_DESC_RESERVED_1A_MSB 37 225 #define MACTX_PHY_DESC_RESERVED_1A_MASK 0x0000002000000000 226 227 228 229 230 #define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 231 #define MACTX_PHY_DESC_STBC_LSB 38 232 #define MACTX_PHY_DESC_STBC_MSB 38 233 #define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 234 235 236 237 238 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 239 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 240 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 241 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 242 243 244 245 246 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 247 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 248 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 249 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 250 251 252 253 254 #define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 255 #define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 256 #define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 257 #define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 258 259 260 261 262 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 263 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 264 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 265 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 266 267 268 269 270 #define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 271 #define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 272 #define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 273 #define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 274 275 276 277 278 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 279 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 280 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 281 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 282 283 284 285 286 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 287 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 288 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 289 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 290 291 292 293 294 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 295 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 296 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 297 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 298 299 300 301 302 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 303 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 304 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 305 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 306 307 308 309 310 #define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 311 #define MACTX_PHY_DESC_NDP_LSB 0 312 #define MACTX_PHY_DESC_NDP_MSB 1 313 #define MACTX_PHY_DESC_NDP_MASK 0x0000000000000003 314 315 316 317 318 #define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 319 #define MACTX_PHY_DESC_UL_FLAG_LSB 2 320 #define MACTX_PHY_DESC_UL_FLAG_MSB 2 321 #define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000004 322 323 324 325 326 #define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 327 #define MACTX_PHY_DESC_TRIGGERED_LSB 3 328 #define MACTX_PHY_DESC_TRIGGERED_MSB 3 329 #define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000008 330 331 332 333 334 #define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 335 #define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 336 #define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 337 #define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x0000000000000070 338 339 340 341 342 #define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 343 #define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 344 #define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 345 #define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x0000000000007f80 346 347 348 349 350 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 351 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 352 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 353 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000038000 354 355 356 357 358 #define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 359 #define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 360 #define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 361 #define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000040000 362 363 364 365 366 #define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 367 #define MACTX_PHY_DESC_RESERVED_2A_LSB 19 368 #define MACTX_PHY_DESC_RESERVED_2A_MSB 20 369 #define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000180000 370 371 372 373 374 #define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 375 #define MACTX_PHY_DESC_NSS_LSB 21 376 #define MACTX_PHY_DESC_NSS_MSB 23 377 #define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 378 379 380 381 382 #define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 383 #define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 384 #define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 385 #define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 386 387 388 389 390 #define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 391 #define MACTX_PHY_DESC_RESERVED_2B_LSB 27 392 #define MACTX_PHY_DESC_RESERVED_2B_MSB 28 393 #define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 394 395 396 397 398 #define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 399 #define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 400 #define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 401 #define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 402 403 404 405 406 #define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 407 #define MACTX_PHY_DESC_MU_NDP_LSB 30 408 #define MACTX_PHY_DESC_MU_NDP_MSB 30 409 #define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 410 411 412 413 414 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 415 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 416 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 417 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 418 419 420 421 422 #define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 423 #define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 424 #define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 425 #define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 426 427 428 429 430 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 431 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 432 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 433 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 434 435 436 437 438 #define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 439 #define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 440 #define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 441 #define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 442 443 444 445 446 #define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 447 #define MACTX_PHY_DESC_ANT_SEL_LSB 42 448 #define MACTX_PHY_DESC_ANT_SEL_MSB 42 449 #define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 450 451 452 453 454 #define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 455 #define MACTX_PHY_DESC_CP_SETTING_LSB 43 456 #define MACTX_PHY_DESC_CP_SETTING_MSB 44 457 #define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 458 459 460 461 462 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 463 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 464 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 465 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 466 467 468 469 470 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 471 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 472 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 473 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 474 475 476 477 478 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 479 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 480 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 481 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 482 483 484 485 486 #define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 487 #define MACTX_PHY_DESC_LTF_SIZE_LSB 51 488 #define MACTX_PHY_DESC_LTF_SIZE_MSB 52 489 #define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 490 491 492 493 494 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 495 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 496 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 497 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 498 499 500 501 502 #define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 503 #define MACTX_PHY_DESC_RESERVED_3C_LSB 57 504 #define MACTX_PHY_DESC_RESERVED_3C_MSB 57 505 #define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 506 507 508 509 510 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 511 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 512 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 513 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 514 515 516 517 #endif 518