1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _MACTX_USER_DESC_COMMON_H_ 20 #define _MACTX_USER_DESC_COMMON_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "unallocated_ru_160_info.h" 25 #include "ru_allocation_160_info.h" 26 #define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 27 28 #define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 29 30 31 struct mactx_user_desc_common { 32 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 33 uint32_t num_users : 6, 34 reserved_0b : 5, 35 ltf_size : 2, 36 reserved_0c : 3, 37 he_stf_long : 1, 38 reserved_0d : 7, 39 num_users_he_sigb_band0 : 8; 40 uint32_t num_ltf_symbols : 3, 41 reserved_1a : 5, 42 num_users_he_sigb_band1 : 8, 43 reserved_1b : 16; 44 uint32_t packet_extension_a_factor : 2, 45 packet_extension_pe_disambiguity : 1, 46 packet_extension : 3, 47 reserved : 2, 48 he_sigb_dcm : 1, 49 reserved_2b : 7, 50 he_sigb_compression : 1, 51 reserved_2c : 15; 52 uint32_t he_sigb_0_mcs : 3, 53 reserved_3a : 13, 54 num_he_sigb_sym : 5, 55 center_ru_0 : 1, 56 center_ru_1 : 1, 57 reserved_3b : 1, 58 ftm_en : 1, 59 pe_nss : 3, 60 pe_ltf_size : 2, 61 pe_content : 1, 62 pe_chain_csd_en : 1; 63 struct ru_allocation_160_info ru_allocation_0123_details; 64 struct ru_allocation_160_info ru_allocation_4567_details; 65 struct unallocated_ru_160_info ru_allocation_160_0_details; 66 struct unallocated_ru_160_info ru_allocation_160_1_details; 67 uint32_t num_data_symbols : 16, 68 ndp_ru_tone_set_index : 7, 69 ndp_feedback_status : 1, 70 doppler_indication : 1, 71 reserved_14a : 7; 72 uint32_t spatial_reuse : 16, 73 reserved_15a : 16; 74 #else 75 uint32_t num_users_he_sigb_band0 : 8, 76 reserved_0d : 7, 77 he_stf_long : 1, 78 reserved_0c : 3, 79 ltf_size : 2, 80 reserved_0b : 5, 81 num_users : 6; 82 uint32_t reserved_1b : 16, 83 num_users_he_sigb_band1 : 8, 84 reserved_1a : 5, 85 num_ltf_symbols : 3; 86 uint32_t reserved_2c : 15, 87 he_sigb_compression : 1, 88 reserved_2b : 7, 89 he_sigb_dcm : 1, 90 reserved : 2, 91 packet_extension : 3, 92 packet_extension_pe_disambiguity : 1, 93 packet_extension_a_factor : 2; 94 uint32_t pe_chain_csd_en : 1, 95 pe_content : 1, 96 pe_ltf_size : 2, 97 pe_nss : 3, 98 ftm_en : 1, 99 reserved_3b : 1, 100 center_ru_1 : 1, 101 center_ru_0 : 1, 102 num_he_sigb_sym : 5, 103 reserved_3a : 13, 104 he_sigb_0_mcs : 3; 105 struct ru_allocation_160_info ru_allocation_0123_details; 106 struct ru_allocation_160_info ru_allocation_4567_details; 107 struct unallocated_ru_160_info ru_allocation_160_0_details; 108 struct unallocated_ru_160_info ru_allocation_160_1_details; 109 uint32_t reserved_14a : 7, 110 doppler_indication : 1, 111 ndp_feedback_status : 1, 112 ndp_ru_tone_set_index : 7, 113 num_data_symbols : 16; 114 uint32_t reserved_15a : 16, 115 spatial_reuse : 16; 116 #endif 117 }; 118 119 120 121 122 #define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 123 #define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 124 #define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 125 #define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f 126 127 128 129 130 #define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 131 #define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 132 #define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 133 #define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 134 135 136 137 138 #define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 139 #define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 140 #define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 141 #define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 142 143 144 145 146 #define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 147 #define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 148 #define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 149 #define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 150 151 152 153 154 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 155 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 156 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 157 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 158 159 160 161 162 #define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 163 #define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 164 #define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 165 #define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 166 167 168 169 170 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 171 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 172 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 173 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 174 175 176 177 178 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 179 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 180 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 181 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 182 183 184 185 186 #define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 187 #define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 188 #define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 189 #define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 190 191 192 193 194 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 195 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 196 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 197 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 198 199 200 201 202 #define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 203 #define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 204 #define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 205 #define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 206 207 208 209 210 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 211 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 212 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 213 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 214 215 216 217 218 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 219 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 220 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 221 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 222 223 224 225 226 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 227 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 228 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 229 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 230 231 232 233 234 #define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 235 #define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 236 #define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 237 #define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 238 239 240 241 242 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 243 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 244 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 245 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 246 247 248 249 250 #define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 251 #define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 252 #define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 253 #define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 254 255 256 257 258 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 259 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 260 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 261 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 262 263 264 265 266 #define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 267 #define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 268 #define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 269 #define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 270 271 272 273 274 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 275 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 276 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 277 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 278 279 280 281 282 #define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 283 #define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 284 #define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 285 #define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 286 287 288 289 290 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 291 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 292 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 293 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 294 295 296 297 298 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 299 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 300 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 301 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 302 303 304 305 306 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 307 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 308 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 309 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 310 311 312 313 314 #define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 315 #define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 316 #define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 317 #define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 318 319 320 321 322 #define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 323 #define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 324 #define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 325 #define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 326 327 328 329 330 #define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 331 #define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 332 #define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 333 #define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 334 335 336 337 338 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 339 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 340 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 341 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 342 343 344 345 346 #define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 347 #define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 348 #define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 349 #define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 350 351 352 353 354 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 355 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 356 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 357 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 358 359 360 361 362 363 364 365 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 366 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 367 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 368 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff 369 370 371 372 373 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 374 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 375 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 376 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 377 378 379 380 381 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 382 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 383 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 384 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 385 386 387 388 389 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 390 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 391 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 392 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 393 394 395 396 397 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 398 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 399 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 400 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 401 402 403 404 405 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 406 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 407 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 408 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 409 410 411 412 413 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 414 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 415 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 416 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 417 418 419 420 421 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 422 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 423 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 424 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 425 426 427 428 429 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 430 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 431 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 432 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff 433 434 435 436 437 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 438 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 439 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 440 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 441 442 443 444 445 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 446 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 447 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 448 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 449 450 451 452 453 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 454 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 455 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 456 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 457 458 459 460 461 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 462 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 463 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 464 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 465 466 467 468 469 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 470 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 471 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 472 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 473 474 475 476 477 478 479 480 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 481 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 482 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 483 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff 484 485 486 487 488 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 489 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 490 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 491 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 492 493 494 495 496 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 497 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 498 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 499 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 500 501 502 503 504 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 505 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 506 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 507 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 508 509 510 511 512 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 513 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 514 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 515 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 516 517 518 519 520 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 521 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 522 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 523 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 524 525 526 527 528 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 529 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 530 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 531 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 532 533 534 535 536 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 537 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 538 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 539 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 540 541 542 543 544 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 545 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 546 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 547 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff 548 549 550 551 552 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 553 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 554 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 555 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 556 557 558 559 560 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 561 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 562 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 563 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 564 565 566 567 568 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 569 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 570 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 571 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 572 573 574 575 576 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 577 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 578 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 579 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 580 581 582 583 584 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 585 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 586 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 587 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 588 589 590 591 592 593 594 595 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 596 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 597 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 598 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff 599 600 601 602 603 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 604 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 605 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 606 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 607 608 609 610 611 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 612 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 613 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 614 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 615 616 617 618 619 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 620 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 621 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 622 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 623 624 625 626 627 628 629 630 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 631 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 632 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 633 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 634 635 636 637 638 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 639 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 640 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 641 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 642 643 644 645 646 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 647 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 648 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 649 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 650 651 652 653 654 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 655 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 656 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 657 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 658 659 660 661 662 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 663 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 664 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 665 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff 666 667 668 669 670 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 671 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 672 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 673 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 674 675 676 677 678 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 679 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 680 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 681 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 682 683 684 685 686 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 687 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 688 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 689 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 690 691 692 693 694 #define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 695 #define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 696 #define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 697 #define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 698 699 700 701 702 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 703 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 704 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 705 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 706 707 708 709 710 #define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 711 #define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 48 712 #define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 713 #define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff000000000000 714 715 716 717 #endif 718