1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _MACTX_USER_DESC_PER_USER_H_ 20 #define _MACTX_USER_DESC_PER_USER_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4 25 26 #define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 2 27 28 29 struct mactx_user_desc_per_user { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t psdu_length : 24, 32 reserved_0a : 8; 33 uint32_t ru_start_index : 8, 34 ru_size : 4, 35 reserved_1b : 4, 36 ofdma_mu_mimo_enabled : 1, 37 nss : 3, 38 stream_offset : 3, 39 reserved_1c : 1, 40 mcs : 4, 41 dcm : 1, 42 reserved_1d : 3; 43 uint32_t fec_type : 1, 44 reserved_2a : 7, 45 user_bf_type : 2, 46 reserved_2b : 6, 47 drop_user_cbf : 1, 48 reserved_2c : 7, 49 ldpc_extra_symbol : 1, 50 force_extra_symbol : 1, 51 reserved_2d : 6; 52 uint32_t sw_peer_id : 16, 53 per_user_subband_mask : 16; 54 #else 55 uint32_t reserved_0a : 8, 56 psdu_length : 24; 57 uint32_t reserved_1d : 3, 58 dcm : 1, 59 mcs : 4, 60 reserved_1c : 1, 61 stream_offset : 3, 62 nss : 3, 63 ofdma_mu_mimo_enabled : 1, 64 reserved_1b : 4, 65 ru_size : 4, 66 ru_start_index : 8; 67 uint32_t reserved_2d : 6, 68 force_extra_symbol : 1, 69 ldpc_extra_symbol : 1, 70 reserved_2c : 7, 71 drop_user_cbf : 1, 72 reserved_2b : 6, 73 user_bf_type : 2, 74 reserved_2a : 7, 75 fec_type : 1; 76 uint32_t per_user_subband_mask : 16, 77 sw_peer_id : 16; 78 #endif 79 }; 80 81 82 83 84 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 85 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 86 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 87 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff 88 89 90 91 92 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 93 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 94 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 95 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 96 97 98 99 100 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 101 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 102 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 103 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 104 105 106 107 108 #define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 109 #define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 110 #define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 111 #define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 112 113 114 115 116 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 117 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 118 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 119 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 120 121 122 123 124 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 125 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 126 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 127 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 128 129 130 131 132 #define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 133 #define MACTX_USER_DESC_PER_USER_NSS_LSB 49 134 #define MACTX_USER_DESC_PER_USER_NSS_MSB 51 135 #define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 136 137 138 139 140 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 141 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 142 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 143 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 144 145 146 147 148 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 149 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 150 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 151 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 152 153 154 155 156 #define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 157 #define MACTX_USER_DESC_PER_USER_MCS_LSB 56 158 #define MACTX_USER_DESC_PER_USER_MCS_MSB 59 159 #define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f00000000000000 160 161 162 163 164 #define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 165 #define MACTX_USER_DESC_PER_USER_DCM_LSB 60 166 #define MACTX_USER_DESC_PER_USER_DCM_MSB 60 167 #define MACTX_USER_DESC_PER_USER_DCM_MASK 0x1000000000000000 168 169 170 171 172 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 173 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 61 174 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 175 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe000000000000000 176 177 178 179 180 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 181 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 182 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 183 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 184 185 186 187 188 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 189 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 190 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7 191 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x00000000000000fe 192 193 194 195 196 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 197 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 198 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 199 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 200 201 202 203 204 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 205 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10 206 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 207 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x000000000000fc00 208 209 210 211 212 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 213 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 214 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 215 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 216 217 218 219 220 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x0000000000000008 221 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17 222 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23 223 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x0000000000fe0000 224 225 226 227 228 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 229 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 230 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 231 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 232 233 234 235 236 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 237 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 238 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 239 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 240 241 242 243 244 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 245 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26 246 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 247 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000fc000000 248 249 250 251 252 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 253 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 254 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 255 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 256 257 258 259 260 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 261 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 262 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 263 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 264 265 266 267 #endif 268