1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _OFDMA_TRIGGER_DETAILS_H_ 20 #define _OFDMA_TRIGGER_DETAILS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "mlo_sta_id_details.h" 25 #define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22 26 27 #define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 11 28 29 30 struct ofdma_trigger_details { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t ax_trigger_source : 1, 33 rx_trigger_frame_user_source : 2, 34 received_bandwidth : 3, 35 txop_duration_all_ones : 1, 36 eht_trigger_response : 1, 37 pre_rssi_comb : 8, 38 rssi_comb : 8, 39 rxpcu_pcie_l0_req_duration : 8; 40 uint32_t he_trigger_ul_ppdu_length : 5, 41 he_trigger_ru_allocation : 8, 42 he_trigger_dl_tx_power : 5, 43 he_trigger_ul_target_rssi : 5, 44 he_trigger_ul_mcs : 2, 45 he_trigger_reserved : 1, 46 bss_color : 6; 47 uint32_t trigger_type : 4, 48 lsig_response_length : 12, 49 cascade_indication : 1, 50 carrier_sense : 1, 51 bandwidth : 2, 52 cp_ltf_size : 2, 53 mu_mimo_ltf_mode : 1, 54 number_of_ltfs : 3, 55 stbc : 1, 56 ldpc_extra_symbol : 1, 57 ap_tx_power_lsb_part : 4; 58 uint32_t ap_tx_power_msb_part : 2, 59 packet_extension_a_factor : 2, 60 packet_extension_pe_disambiguity : 1, 61 spatial_reuse : 16, 62 doppler : 1, 63 he_siga_reserved : 9, 64 reserved_3b : 1; 65 uint32_t aid12 : 12, 66 ru_allocation : 9, 67 mcs : 4, 68 dcm : 1, 69 start_spatial_stream : 3, 70 number_of_spatial_stream : 3; 71 uint32_t target_rssi : 7, 72 coding_type : 1, 73 mpdu_mu_spacing_factor : 2, 74 tid_aggregation_limit : 3, 75 reserved_5b : 1, 76 prefered_ac : 2, 77 bar_control_ack_policy : 1, 78 bar_control_multi_tid : 1, 79 bar_control_compressed_bitmap : 1, 80 bar_control_reserved : 9, 81 bar_control_tid_info : 4; 82 uint32_t nr0_per_tid_info_reserved : 12, 83 nr0_per_tid_info_tid_value : 4, 84 nr0_start_seq_ctrl_frag_number : 4, 85 nr0_start_seq_ctrl_start_seq_number : 12; 86 uint32_t nr1_per_tid_info_reserved : 12, 87 nr1_per_tid_info_tid_value : 4, 88 nr1_start_seq_ctrl_frag_number : 4, 89 nr1_start_seq_ctrl_start_seq_number : 12; 90 uint32_t nr2_per_tid_info_reserved : 12, 91 nr2_per_tid_info_tid_value : 4, 92 nr2_start_seq_ctrl_frag_number : 4, 93 nr2_start_seq_ctrl_start_seq_number : 12; 94 uint32_t nr3_per_tid_info_reserved : 12, 95 nr3_per_tid_info_tid_value : 4, 96 nr3_start_seq_ctrl_frag_number : 4, 97 nr3_start_seq_ctrl_start_seq_number : 12; 98 uint32_t nr4_per_tid_info_reserved : 12, 99 nr4_per_tid_info_tid_value : 4, 100 nr4_start_seq_ctrl_frag_number : 4, 101 nr4_start_seq_ctrl_start_seq_number : 12; 102 uint32_t nr5_per_tid_info_reserved : 12, 103 nr5_per_tid_info_tid_value : 4, 104 nr5_start_seq_ctrl_frag_number : 4, 105 nr5_start_seq_ctrl_start_seq_number : 12; 106 uint32_t nr6_per_tid_info_reserved : 12, 107 nr6_per_tid_info_tid_value : 4, 108 nr6_start_seq_ctrl_frag_number : 4, 109 nr6_start_seq_ctrl_start_seq_number : 12; 110 uint32_t nr7_per_tid_info_reserved : 12, 111 nr7_per_tid_info_tid_value : 4, 112 nr7_start_seq_ctrl_frag_number : 4, 113 nr7_start_seq_ctrl_start_seq_number : 12; 114 uint32_t fb_segment_retransmission_bitmap : 8, 115 reserved_14a : 2, 116 u_sig_puncture_pattern_encoding : 6, 117 dot11be_puncture_bitmap : 16; 118 uint32_t rx_chain_mask : 8, 119 rx_duration_field : 16, 120 scrambler_seed : 7, 121 rx_chain_mask_type : 1; 122 struct mlo_sta_id_details mlo_sta_id_details_rx; 123 uint16_t normalized_pre_rssi_comb : 8, 124 normalized_rssi_comb : 8; 125 uint32_t sw_peer_id : 16, 126 response_tx_duration : 16; 127 uint32_t ranging_trigger_subtype : 4, 128 tbr_trigger_common_info_79_68 : 12, 129 tbr_trigger_sound_reserved_20_12 : 9, 130 i2r_rep : 3, 131 tbr_trigger_sound_reserved_25_24 : 2, 132 reserved_18a : 1, 133 qos_null_only_response_tx : 1; 134 uint32_t tbr_trigger_sound_sac : 16, 135 reserved_19a : 8, 136 u_sig_reserved2 : 5, 137 reserved_19b : 3; 138 uint32_t eht_special_aid12 : 12, 139 phy_version : 3, 140 bandwidth_ext : 2, 141 eht_spatial_reuse : 8, 142 u_sig_reserved1 : 7; 143 uint32_t eht_trigger_special_user_info_71_40 : 32; 144 #else 145 uint32_t rxpcu_pcie_l0_req_duration : 8, 146 rssi_comb : 8, 147 pre_rssi_comb : 8, 148 eht_trigger_response : 1, 149 txop_duration_all_ones : 1, 150 received_bandwidth : 3, 151 rx_trigger_frame_user_source : 2, 152 ax_trigger_source : 1; 153 uint32_t bss_color : 6, 154 he_trigger_reserved : 1, 155 he_trigger_ul_mcs : 2, 156 he_trigger_ul_target_rssi : 5, 157 he_trigger_dl_tx_power : 5, 158 he_trigger_ru_allocation : 8, 159 he_trigger_ul_ppdu_length : 5; 160 uint32_t ap_tx_power_lsb_part : 4, 161 ldpc_extra_symbol : 1, 162 stbc : 1, 163 number_of_ltfs : 3, 164 mu_mimo_ltf_mode : 1, 165 cp_ltf_size : 2, 166 bandwidth : 2, 167 carrier_sense : 1, 168 cascade_indication : 1, 169 lsig_response_length : 12, 170 trigger_type : 4; 171 uint32_t reserved_3b : 1, 172 he_siga_reserved : 9, 173 doppler : 1, 174 spatial_reuse : 16, 175 packet_extension_pe_disambiguity : 1, 176 packet_extension_a_factor : 2, 177 ap_tx_power_msb_part : 2; 178 uint32_t number_of_spatial_stream : 3, 179 start_spatial_stream : 3, 180 dcm : 1, 181 mcs : 4, 182 ru_allocation : 9, 183 aid12 : 12; 184 uint32_t bar_control_tid_info : 4, 185 bar_control_reserved : 9, 186 bar_control_compressed_bitmap : 1, 187 bar_control_multi_tid : 1, 188 bar_control_ack_policy : 1, 189 prefered_ac : 2, 190 reserved_5b : 1, 191 tid_aggregation_limit : 3, 192 mpdu_mu_spacing_factor : 2, 193 coding_type : 1, 194 target_rssi : 7; 195 uint32_t nr0_start_seq_ctrl_start_seq_number : 12, 196 nr0_start_seq_ctrl_frag_number : 4, 197 nr0_per_tid_info_tid_value : 4, 198 nr0_per_tid_info_reserved : 12; 199 uint32_t nr1_start_seq_ctrl_start_seq_number : 12, 200 nr1_start_seq_ctrl_frag_number : 4, 201 nr1_per_tid_info_tid_value : 4, 202 nr1_per_tid_info_reserved : 12; 203 uint32_t nr2_start_seq_ctrl_start_seq_number : 12, 204 nr2_start_seq_ctrl_frag_number : 4, 205 nr2_per_tid_info_tid_value : 4, 206 nr2_per_tid_info_reserved : 12; 207 uint32_t nr3_start_seq_ctrl_start_seq_number : 12, 208 nr3_start_seq_ctrl_frag_number : 4, 209 nr3_per_tid_info_tid_value : 4, 210 nr3_per_tid_info_reserved : 12; 211 uint32_t nr4_start_seq_ctrl_start_seq_number : 12, 212 nr4_start_seq_ctrl_frag_number : 4, 213 nr4_per_tid_info_tid_value : 4, 214 nr4_per_tid_info_reserved : 12; 215 uint32_t nr5_start_seq_ctrl_start_seq_number : 12, 216 nr5_start_seq_ctrl_frag_number : 4, 217 nr5_per_tid_info_tid_value : 4, 218 nr5_per_tid_info_reserved : 12; 219 uint32_t nr6_start_seq_ctrl_start_seq_number : 12, 220 nr6_start_seq_ctrl_frag_number : 4, 221 nr6_per_tid_info_tid_value : 4, 222 nr6_per_tid_info_reserved : 12; 223 uint32_t nr7_start_seq_ctrl_start_seq_number : 12, 224 nr7_start_seq_ctrl_frag_number : 4, 225 nr7_per_tid_info_tid_value : 4, 226 nr7_per_tid_info_reserved : 12; 227 uint32_t dot11be_puncture_bitmap : 16, 228 u_sig_puncture_pattern_encoding : 6, 229 reserved_14a : 2, 230 fb_segment_retransmission_bitmap : 8; 231 uint32_t rx_chain_mask_type : 1, 232 scrambler_seed : 7, 233 rx_duration_field : 16, 234 rx_chain_mask : 8; 235 uint32_t normalized_rssi_comb : 8, 236 normalized_pre_rssi_comb : 8; 237 struct mlo_sta_id_details mlo_sta_id_details_rx; 238 uint32_t response_tx_duration : 16, 239 sw_peer_id : 16; 240 uint32_t qos_null_only_response_tx : 1, 241 reserved_18a : 1, 242 tbr_trigger_sound_reserved_25_24 : 2, 243 i2r_rep : 3, 244 tbr_trigger_sound_reserved_20_12 : 9, 245 tbr_trigger_common_info_79_68 : 12, 246 ranging_trigger_subtype : 4; 247 uint32_t reserved_19b : 3, 248 u_sig_reserved2 : 5, 249 reserved_19a : 8, 250 tbr_trigger_sound_sac : 16; 251 uint32_t u_sig_reserved1 : 7, 252 eht_spatial_reuse : 8, 253 bandwidth_ext : 2, 254 phy_version : 3, 255 eht_special_aid12 : 12; 256 uint32_t eht_trigger_special_user_info_71_40 : 32; 257 #endif 258 }; 259 260 261 262 263 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 264 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 265 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 266 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 267 268 269 270 271 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 272 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 273 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 274 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 275 276 277 278 279 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 280 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 281 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 282 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 283 284 285 286 287 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 288 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 289 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 290 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 291 292 293 294 295 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 296 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 297 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 298 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 299 300 301 302 303 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 304 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 305 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 306 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 307 308 309 310 311 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 312 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 313 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 314 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 315 316 317 318 319 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 320 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 321 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 322 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 323 324 325 326 327 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 328 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 329 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 330 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 331 332 333 334 335 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 336 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 337 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 338 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 339 340 341 342 343 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 344 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 345 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 346 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 347 348 349 350 351 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 352 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 353 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 354 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 355 356 357 358 359 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 360 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 361 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 362 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 363 364 365 366 367 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 368 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 369 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 370 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 371 372 373 374 375 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 376 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 377 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 378 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 379 380 381 382 383 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 384 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 385 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 386 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f 387 388 389 390 391 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 392 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 393 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 394 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 395 396 397 398 399 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 400 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 401 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 402 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 403 404 405 406 407 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 408 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 409 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 410 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 411 412 413 414 415 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 416 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 417 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 418 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 419 420 421 422 423 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 424 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 425 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 426 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 427 428 429 430 431 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 432 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 433 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 434 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 435 436 437 438 439 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 440 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 441 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 442 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 443 444 445 446 447 #define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 448 #define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 449 #define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 450 #define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 451 452 453 454 455 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 456 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 457 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 458 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 459 460 461 462 463 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 464 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 465 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 466 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 467 468 469 470 471 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 472 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 473 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 474 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 475 476 477 478 479 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 480 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 481 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 482 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 483 484 485 486 487 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 488 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 489 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 490 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 491 492 493 494 495 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 496 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 497 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 498 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 499 500 501 502 503 #define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 504 #define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 505 #define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 506 #define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 507 508 509 510 511 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 512 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 513 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 514 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 515 516 517 518 519 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 520 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 521 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 522 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 523 524 525 526 527 #define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 528 #define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 529 #define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 530 #define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff 531 532 533 534 535 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 536 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 537 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 538 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 539 540 541 542 543 #define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 544 #define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 545 #define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 546 #define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 547 548 549 550 551 #define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 552 #define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 553 #define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 554 #define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 555 556 557 558 559 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 560 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 561 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 562 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 563 564 565 566 567 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 568 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 569 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 570 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 571 572 573 574 575 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 576 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 577 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 578 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 579 580 581 582 583 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 584 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 585 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 586 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 587 588 589 590 591 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 592 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 593 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 594 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 595 596 597 598 599 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 600 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 601 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 602 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 603 604 605 606 607 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 608 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 609 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 610 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 611 612 613 614 615 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 616 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 617 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 618 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 619 620 621 622 623 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 624 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 625 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 626 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 627 628 629 630 631 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 632 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 633 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 634 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 635 636 637 638 639 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 640 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 641 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 642 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 643 644 645 646 647 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 648 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 649 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 650 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 651 652 653 654 655 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 656 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 657 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 658 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 659 660 661 662 663 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 664 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 665 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 666 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff 667 668 669 670 671 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 672 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 673 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 674 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 675 676 677 678 679 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 680 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 681 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 682 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 683 684 685 686 687 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 688 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 689 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 690 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 691 692 693 694 695 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 696 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 697 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 698 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 699 700 701 702 703 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 704 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 705 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 706 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 707 708 709 710 711 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 712 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 713 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 714 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 715 716 717 718 719 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 720 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 721 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 722 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 723 724 725 726 727 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 728 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 729 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 730 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff 731 732 733 734 735 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 736 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 737 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 738 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 739 740 741 742 743 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 744 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 745 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 746 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 747 748 749 750 751 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 752 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 753 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 754 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 755 756 757 758 759 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 760 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 761 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 762 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 763 764 765 766 767 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 768 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 769 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 770 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 771 772 773 774 775 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 776 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 777 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 778 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 779 780 781 782 783 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 784 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 785 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 786 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 787 788 789 790 791 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 792 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 793 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 794 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff 795 796 797 798 799 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 800 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 801 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 802 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 803 804 805 806 807 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 808 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 809 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 810 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 811 812 813 814 815 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 816 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 817 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 818 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 819 820 821 822 823 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 824 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 825 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 826 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 827 828 829 830 831 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 832 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 833 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 834 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 835 836 837 838 839 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 840 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 841 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 842 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 843 844 845 846 847 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 848 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 849 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 850 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 851 852 853 854 855 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 856 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 857 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 858 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff 859 860 861 862 863 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 864 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 865 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 866 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 867 868 869 870 871 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 872 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 873 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 874 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 875 876 877 878 879 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 880 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 881 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 882 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 883 884 885 886 887 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 888 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 889 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 890 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 891 892 893 894 895 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 896 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 897 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 898 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 899 900 901 902 903 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 904 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 905 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 906 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 907 908 909 910 911 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 912 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 913 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 914 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 915 916 917 918 919 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 920 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 921 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 922 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff 923 924 925 926 927 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 928 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 929 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 930 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 931 932 933 934 935 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 936 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 937 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 938 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 939 940 941 942 943 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 944 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 945 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 946 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 947 948 949 950 951 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 952 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 953 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 954 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 955 956 957 958 959 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 960 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 961 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 962 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 963 964 965 966 967 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 968 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 969 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 970 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 971 972 973 974 975 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 976 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 977 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 978 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 979 980 981 982 983 984 985 986 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 987 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 988 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 989 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff 990 991 992 993 994 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 995 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 996 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 997 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 998 999 1000 1001 1002 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 1003 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 1004 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 1005 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 1006 1007 1008 1009 1010 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 1011 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 1012 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 1013 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 1014 1015 1016 1017 1018 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 1019 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 1020 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 1021 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 1022 1023 1024 1025 1026 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 1027 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 1028 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 1029 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 1030 1031 1032 1033 1034 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 1035 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 1036 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 1037 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 1038 1039 1040 1041 1042 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 1043 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 1044 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 1045 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 1046 1047 1048 1049 1050 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 1051 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 1052 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 1053 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 1054 1055 1056 1057 1058 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000048 1059 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0 1060 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3 1061 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000000f 1062 1063 1064 1065 1066 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 1067 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 1068 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 1069 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 1070 1071 1072 1073 1074 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 1075 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 1076 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 1077 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 1078 1079 1080 1081 1082 #define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 1083 #define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 1084 #define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 1085 #define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 1086 1087 1088 1089 1090 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 1091 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 1092 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 1093 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 1094 1095 1096 1097 1098 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 1099 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 1100 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 1101 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 1102 1103 1104 1105 1106 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 1107 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 1108 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 1109 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 1110 1111 1112 1113 1114 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 1115 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 1116 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 1117 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 1118 1119 1120 1121 1122 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 1123 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 1124 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 1125 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 1126 1127 1128 1129 1130 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 1131 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 1132 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 1133 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 1134 1135 1136 1137 1138 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 1139 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 1140 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 1141 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 1142 1143 1144 1145 1146 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 1147 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 1148 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 1149 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff 1150 1151 1152 1153 1154 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 1155 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 1156 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 1157 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 1158 1159 1160 1161 1162 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 1163 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 1164 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 1165 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 1166 1167 1168 1169 1170 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 1171 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 1172 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 1173 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 1174 1175 1176 1177 1178 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 1179 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 1180 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 1181 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 1182 1183 1184 1185 1186 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 1187 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 1188 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 1189 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 1190 1191 1192 1193 #endif 1194