1*5113495bSYour Name 2*5113495bSYour Name /* 3*5113495bSYour Name * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * SPDX-License-Identifier: ISC 5*5113495bSYour Name */ 6*5113495bSYour Name 7*5113495bSYour Name 8*5113495bSYour Name 9*5113495bSYour Name 10*5113495bSYour Name 11*5113495bSYour Name 12*5113495bSYour Name 13*5113495bSYour Name 14*5113495bSYour Name 15*5113495bSYour Name 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name #ifndef _REO_FLUSH_CACHE_H_ 20*5113495bSYour Name #define _REO_FLUSH_CACHE_H_ 21*5113495bSYour Name #if !defined(__ASSEMBLER__) 22*5113495bSYour Name #endif 23*5113495bSYour Name 24*5113495bSYour Name #include "uniform_reo_cmd_header.h" 25*5113495bSYour Name #define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 26*5113495bSYour Name 27*5113495bSYour Name #define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 28*5113495bSYour Name 29*5113495bSYour Name 30*5113495bSYour Name struct reo_flush_cache { 31*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32*5113495bSYour Name struct uniform_reo_cmd_header cmd_header; 33*5113495bSYour Name uint32_t flush_addr_31_0 : 32; 34*5113495bSYour Name uint32_t flush_addr_39_32 : 8, 35*5113495bSYour Name forward_all_mpdus_in_queue : 1, 36*5113495bSYour Name release_cache_block_index : 1, 37*5113495bSYour Name cache_block_resource_index : 2, 38*5113495bSYour Name flush_without_invalidate : 1, 39*5113495bSYour Name block_cache_usage_after_flush : 1, 40*5113495bSYour Name flush_entire_cache : 1, 41*5113495bSYour Name flush_queue_1k_desc : 1, 42*5113495bSYour Name reserved_2b : 16; 43*5113495bSYour Name uint32_t reserved_3a : 32; 44*5113495bSYour Name uint32_t reserved_4a : 32; 45*5113495bSYour Name uint32_t reserved_5a : 32; 46*5113495bSYour Name uint32_t reserved_6a : 32; 47*5113495bSYour Name uint32_t reserved_7a : 32; 48*5113495bSYour Name uint32_t reserved_8a : 32; 49*5113495bSYour Name uint32_t tlv64_padding : 32; 50*5113495bSYour Name #else 51*5113495bSYour Name struct uniform_reo_cmd_header cmd_header; 52*5113495bSYour Name uint32_t flush_addr_31_0 : 32; 53*5113495bSYour Name uint32_t reserved_2b : 16, 54*5113495bSYour Name flush_queue_1k_desc : 1, 55*5113495bSYour Name flush_entire_cache : 1, 56*5113495bSYour Name block_cache_usage_after_flush : 1, 57*5113495bSYour Name flush_without_invalidate : 1, 58*5113495bSYour Name cache_block_resource_index : 2, 59*5113495bSYour Name release_cache_block_index : 1, 60*5113495bSYour Name forward_all_mpdus_in_queue : 1, 61*5113495bSYour Name flush_addr_39_32 : 8; 62*5113495bSYour Name uint32_t reserved_3a : 32; 63*5113495bSYour Name uint32_t reserved_4a : 32; 64*5113495bSYour Name uint32_t reserved_5a : 32; 65*5113495bSYour Name uint32_t reserved_6a : 32; 66*5113495bSYour Name uint32_t reserved_7a : 32; 67*5113495bSYour Name uint32_t reserved_8a : 32; 68*5113495bSYour Name uint32_t tlv64_padding : 32; 69*5113495bSYour Name #endif 70*5113495bSYour Name }; 71*5113495bSYour Name 72*5113495bSYour Name 73*5113495bSYour Name 74*5113495bSYour Name 75*5113495bSYour Name 76*5113495bSYour Name 77*5113495bSYour Name 78*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 79*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 80*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 81*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 82*5113495bSYour Name 83*5113495bSYour Name 84*5113495bSYour Name 85*5113495bSYour Name 86*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 87*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 88*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 89*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 90*5113495bSYour Name 91*5113495bSYour Name 92*5113495bSYour Name 93*5113495bSYour Name 94*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 95*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 96*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 97*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 98*5113495bSYour Name 99*5113495bSYour Name 100*5113495bSYour Name 101*5113495bSYour Name 102*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 103*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 104*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 105*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 106*5113495bSYour Name 107*5113495bSYour Name 108*5113495bSYour Name 109*5113495bSYour Name 110*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 111*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 112*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 113*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff 114*5113495bSYour Name 115*5113495bSYour Name 116*5113495bSYour Name 117*5113495bSYour Name 118*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 119*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 120*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 121*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 122*5113495bSYour Name 123*5113495bSYour Name 124*5113495bSYour Name 125*5113495bSYour Name 126*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 127*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 128*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 129*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 130*5113495bSYour Name 131*5113495bSYour Name 132*5113495bSYour Name 133*5113495bSYour Name 134*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 135*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 136*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 137*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 138*5113495bSYour Name 139*5113495bSYour Name 140*5113495bSYour Name 141*5113495bSYour Name 142*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 143*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 144*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 145*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 146*5113495bSYour Name 147*5113495bSYour Name 148*5113495bSYour Name 149*5113495bSYour Name 150*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 151*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 152*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 153*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 154*5113495bSYour Name 155*5113495bSYour Name 156*5113495bSYour Name 157*5113495bSYour Name 158*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 159*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 160*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 161*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 162*5113495bSYour Name 163*5113495bSYour Name 164*5113495bSYour Name 165*5113495bSYour Name 166*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 167*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 168*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 169*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 170*5113495bSYour Name 171*5113495bSYour Name 172*5113495bSYour Name 173*5113495bSYour Name 174*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 175*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 176*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 177*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 178*5113495bSYour Name 179*5113495bSYour Name 180*5113495bSYour Name 181*5113495bSYour Name 182*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 183*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 184*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 185*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 186*5113495bSYour Name 187*5113495bSYour Name 188*5113495bSYour Name 189*5113495bSYour Name 190*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 191*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 192*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 193*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff 194*5113495bSYour Name 195*5113495bSYour Name 196*5113495bSYour Name 197*5113495bSYour Name 198*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 199*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 200*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 201*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 202*5113495bSYour Name 203*5113495bSYour Name 204*5113495bSYour Name 205*5113495bSYour Name 206*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 207*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 208*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 209*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff 210*5113495bSYour Name 211*5113495bSYour Name 212*5113495bSYour Name 213*5113495bSYour Name 214*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 215*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 216*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 217*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 218*5113495bSYour Name 219*5113495bSYour Name 220*5113495bSYour Name 221*5113495bSYour Name 222*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 223*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 224*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 225*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff 226*5113495bSYour Name 227*5113495bSYour Name 228*5113495bSYour Name 229*5113495bSYour Name 230*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 231*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 232*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 233*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 234*5113495bSYour Name 235*5113495bSYour Name 236*5113495bSYour Name 237*5113495bSYour Name #endif 238