1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _REO_FLUSH_CACHE_H_ 20 #define _REO_FLUSH_CACHE_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_cmd_header.h" 25 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 26 27 #define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 28 29 30 struct reo_flush_cache { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct uniform_reo_cmd_header cmd_header; 33 uint32_t flush_addr_31_0 : 32; 34 uint32_t flush_addr_39_32 : 8, 35 forward_all_mpdus_in_queue : 1, 36 release_cache_block_index : 1, 37 cache_block_resource_index : 2, 38 flush_without_invalidate : 1, 39 block_cache_usage_after_flush : 1, 40 flush_entire_cache : 1, 41 flush_queue_1k_desc : 1, 42 reserved_2b : 16; 43 uint32_t reserved_3a : 32; 44 uint32_t reserved_4a : 32; 45 uint32_t reserved_5a : 32; 46 uint32_t reserved_6a : 32; 47 uint32_t reserved_7a : 32; 48 uint32_t reserved_8a : 32; 49 uint32_t tlv64_padding : 32; 50 #else 51 struct uniform_reo_cmd_header cmd_header; 52 uint32_t flush_addr_31_0 : 32; 53 uint32_t reserved_2b : 16, 54 flush_queue_1k_desc : 1, 55 flush_entire_cache : 1, 56 block_cache_usage_after_flush : 1, 57 flush_without_invalidate : 1, 58 cache_block_resource_index : 2, 59 release_cache_block_index : 1, 60 forward_all_mpdus_in_queue : 1, 61 flush_addr_39_32 : 8; 62 uint32_t reserved_3a : 32; 63 uint32_t reserved_4a : 32; 64 uint32_t reserved_5a : 32; 65 uint32_t reserved_6a : 32; 66 uint32_t reserved_7a : 32; 67 uint32_t reserved_8a : 32; 68 uint32_t tlv64_padding : 32; 69 #endif 70 }; 71 72 73 74 75 76 77 78 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 79 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 80 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 81 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 82 83 84 85 86 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 87 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 88 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 89 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 90 91 92 93 94 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 95 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 96 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 97 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 98 99 100 101 102 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 103 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 104 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 105 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 106 107 108 109 110 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 111 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 112 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 113 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff 114 115 116 117 118 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 119 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 120 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 121 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 122 123 124 125 126 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 127 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 128 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 129 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 130 131 132 133 134 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 135 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 136 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 137 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 138 139 140 141 142 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 143 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 144 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 145 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 146 147 148 149 150 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 151 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 152 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 153 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 154 155 156 157 158 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 159 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 160 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 161 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 162 163 164 165 166 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 167 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 168 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 169 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 170 171 172 173 174 #define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 175 #define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 176 #define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 177 #define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 178 179 180 181 182 #define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 183 #define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 184 #define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 185 #define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 186 187 188 189 190 #define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 191 #define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 192 #define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 193 #define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff 194 195 196 197 198 #define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 199 #define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 200 #define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 201 #define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 202 203 204 205 206 #define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 207 #define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 208 #define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 209 #define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff 210 211 212 213 214 #define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 215 #define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 216 #define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 217 #define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 218 219 220 221 222 #define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 223 #define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 224 #define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 225 #define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff 226 227 228 229 230 #define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 231 #define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 232 #define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 233 #define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 234 235 236 237 #endif 238