1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _REO_FLUSH_CACHE_STATUS_H_ 20 #define _REO_FLUSH_CACHE_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_status_header.h" 25 #define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26 26 27 #define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13 28 29 30 struct reo_flush_cache_status { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct uniform_reo_status_header status_header; 33 uint32_t error_detected : 1, 34 block_error_details : 2, 35 reserved_2a : 5, 36 cache_controller_flush_status_hit : 1, 37 cache_controller_flush_status_desc_type : 3, 38 cache_controller_flush_status_client_id : 4, 39 cache_controller_flush_status_error : 2, 40 cache_controller_flush_count : 8, 41 flush_queue_1k_desc : 1, 42 reserved_2b : 5; 43 uint32_t reserved_3a : 32; 44 uint32_t reserved_4a : 32; 45 uint32_t reserved_5a : 32; 46 uint32_t reserved_6a : 32; 47 uint32_t reserved_7a : 32; 48 uint32_t reserved_8a : 32; 49 uint32_t reserved_9a : 32; 50 uint32_t reserved_10a : 32; 51 uint32_t reserved_11a : 32; 52 uint32_t reserved_12a : 32; 53 uint32_t reserved_13a : 32; 54 uint32_t reserved_14a : 32; 55 uint32_t reserved_15a : 32; 56 uint32_t reserved_16a : 32; 57 uint32_t reserved_17a : 32; 58 uint32_t reserved_18a : 32; 59 uint32_t reserved_19a : 32; 60 uint32_t reserved_20a : 32; 61 uint32_t reserved_21a : 32; 62 uint32_t reserved_22a : 32; 63 uint32_t reserved_23a : 32; 64 uint32_t reserved_24a : 32; 65 uint32_t reserved_25a : 28, 66 looping_count : 4; 67 #else 68 struct uniform_reo_status_header status_header; 69 uint32_t reserved_2b : 5, 70 flush_queue_1k_desc : 1, 71 cache_controller_flush_count : 8, 72 cache_controller_flush_status_error : 2, 73 cache_controller_flush_status_client_id : 4, 74 cache_controller_flush_status_desc_type : 3, 75 cache_controller_flush_status_hit : 1, 76 reserved_2a : 5, 77 block_error_details : 2, 78 error_detected : 1; 79 uint32_t reserved_3a : 32; 80 uint32_t reserved_4a : 32; 81 uint32_t reserved_5a : 32; 82 uint32_t reserved_6a : 32; 83 uint32_t reserved_7a : 32; 84 uint32_t reserved_8a : 32; 85 uint32_t reserved_9a : 32; 86 uint32_t reserved_10a : 32; 87 uint32_t reserved_11a : 32; 88 uint32_t reserved_12a : 32; 89 uint32_t reserved_13a : 32; 90 uint32_t reserved_14a : 32; 91 uint32_t reserved_15a : 32; 92 uint32_t reserved_16a : 32; 93 uint32_t reserved_17a : 32; 94 uint32_t reserved_18a : 32; 95 uint32_t reserved_19a : 32; 96 uint32_t reserved_20a : 32; 97 uint32_t reserved_21a : 32; 98 uint32_t reserved_22a : 32; 99 uint32_t reserved_23a : 32; 100 uint32_t reserved_24a : 32; 101 uint32_t looping_count : 4, 102 reserved_25a : 28; 103 #endif 104 }; 105 106 107 108 109 110 111 112 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 113 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 114 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 115 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 116 117 118 119 120 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 121 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 122 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 123 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 124 125 126 127 128 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 129 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 130 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 131 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 132 133 134 135 136 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 137 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 138 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 139 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 140 141 142 143 144 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 145 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 146 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 147 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 148 149 150 151 152 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 153 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 154 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 155 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 156 157 158 159 160 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008 161 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 162 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 163 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006 164 165 166 167 168 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 169 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 170 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 171 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8 172 173 174 175 176 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008 177 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 178 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 179 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100 180 181 182 183 184 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008 185 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 186 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 187 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00 188 189 190 191 192 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008 193 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 194 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 195 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000 196 197 198 199 200 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008 201 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 202 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 203 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000 204 205 206 207 208 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008 209 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 210 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 211 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000 212 213 214 215 216 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 217 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 218 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 219 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000 220 221 222 223 224 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 225 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 226 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 227 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000 228 229 230 231 232 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 233 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32 234 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63 235 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 236 237 238 239 240 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 241 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 242 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 243 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 244 245 246 247 248 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 249 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32 250 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63 251 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 252 253 254 255 256 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 257 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 258 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 259 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 260 261 262 263 264 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 265 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32 266 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63 267 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 268 269 270 271 272 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 273 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 274 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 275 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 276 277 278 279 280 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 281 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32 282 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63 283 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 284 285 286 287 288 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 289 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 290 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 291 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 292 293 294 295 296 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 297 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32 298 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63 299 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 300 301 302 303 304 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 305 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 306 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 307 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 308 309 310 311 312 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 313 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32 314 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63 315 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 316 317 318 319 320 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 321 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 322 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 323 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 324 325 326 327 328 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 329 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32 330 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63 331 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 332 333 334 335 336 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 337 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 338 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 339 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 340 341 342 343 344 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 345 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32 346 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63 347 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 348 349 350 351 352 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 353 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 354 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 355 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 356 357 358 359 360 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 361 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32 362 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63 363 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 364 365 366 367 368 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 369 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 370 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 371 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 372 373 374 375 376 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 377 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32 378 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63 379 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 380 381 382 383 384 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 385 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 386 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 387 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 388 389 390 391 392 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 393 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32 394 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63 395 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 396 397 398 399 400 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 401 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 402 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 403 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 404 405 406 407 408 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 409 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32 410 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59 411 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 412 413 414 415 416 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 417 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60 418 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63 419 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 420 421 422 423 #endif 424