1*5113495bSYour Name 2*5113495bSYour Name /* 3*5113495bSYour Name * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * SPDX-License-Identifier: ISC 5*5113495bSYour Name */ 6*5113495bSYour Name 7*5113495bSYour Name 8*5113495bSYour Name 9*5113495bSYour Name 10*5113495bSYour Name 11*5113495bSYour Name 12*5113495bSYour Name 13*5113495bSYour Name 14*5113495bSYour Name 15*5113495bSYour Name 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name #ifndef _REO_FLUSH_QUEUE_H_ 20*5113495bSYour Name #define _REO_FLUSH_QUEUE_H_ 21*5113495bSYour Name #if !defined(__ASSEMBLER__) 22*5113495bSYour Name #endif 23*5113495bSYour Name 24*5113495bSYour Name #include "uniform_reo_cmd_header.h" 25*5113495bSYour Name #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10 26*5113495bSYour Name 27*5113495bSYour Name #define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5 28*5113495bSYour Name 29*5113495bSYour Name 30*5113495bSYour Name struct reo_flush_queue { 31*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32*5113495bSYour Name struct uniform_reo_cmd_header cmd_header; 33*5113495bSYour Name uint32_t flush_desc_addr_31_0 : 32; 34*5113495bSYour Name uint32_t flush_desc_addr_39_32 : 8, 35*5113495bSYour Name block_desc_addr_usage_after_flush : 1, 36*5113495bSYour Name block_resource_index : 2, 37*5113495bSYour Name reserved_2a : 21; 38*5113495bSYour Name uint32_t reserved_3a : 32; 39*5113495bSYour Name uint32_t reserved_4a : 32; 40*5113495bSYour Name uint32_t reserved_5a : 32; 41*5113495bSYour Name uint32_t reserved_6a : 32; 42*5113495bSYour Name uint32_t reserved_7a : 32; 43*5113495bSYour Name uint32_t reserved_8a : 32; 44*5113495bSYour Name uint32_t tlv64_padding : 32; 45*5113495bSYour Name #else 46*5113495bSYour Name struct uniform_reo_cmd_header cmd_header; 47*5113495bSYour Name uint32_t flush_desc_addr_31_0 : 32; 48*5113495bSYour Name uint32_t reserved_2a : 21, 49*5113495bSYour Name block_resource_index : 2, 50*5113495bSYour Name block_desc_addr_usage_after_flush : 1, 51*5113495bSYour Name flush_desc_addr_39_32 : 8; 52*5113495bSYour Name uint32_t reserved_3a : 32; 53*5113495bSYour Name uint32_t reserved_4a : 32; 54*5113495bSYour Name uint32_t reserved_5a : 32; 55*5113495bSYour Name uint32_t reserved_6a : 32; 56*5113495bSYour Name uint32_t reserved_7a : 32; 57*5113495bSYour Name uint32_t reserved_8a : 32; 58*5113495bSYour Name uint32_t tlv64_padding : 32; 59*5113495bSYour Name #endif 60*5113495bSYour Name }; 61*5113495bSYour Name 62*5113495bSYour Name 63*5113495bSYour Name 64*5113495bSYour Name 65*5113495bSYour Name 66*5113495bSYour Name 67*5113495bSYour Name 68*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 69*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 70*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 71*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 72*5113495bSYour Name 73*5113495bSYour Name 74*5113495bSYour Name 75*5113495bSYour Name 76*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 77*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 78*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 79*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 80*5113495bSYour Name 81*5113495bSYour Name 82*5113495bSYour Name 83*5113495bSYour Name 84*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 85*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 86*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 87*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 88*5113495bSYour Name 89*5113495bSYour Name 90*5113495bSYour Name 91*5113495bSYour Name 92*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000 93*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32 94*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63 95*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000 96*5113495bSYour Name 97*5113495bSYour Name 98*5113495bSYour Name 99*5113495bSYour Name 100*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008 101*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 102*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 103*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff 104*5113495bSYour Name 105*5113495bSYour Name 106*5113495bSYour Name 107*5113495bSYour Name 108*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 109*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 110*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 111*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100 112*5113495bSYour Name 113*5113495bSYour Name 114*5113495bSYour Name 115*5113495bSYour Name 116*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 117*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 118*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 119*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600 120*5113495bSYour Name 121*5113495bSYour Name 122*5113495bSYour Name 123*5113495bSYour Name 124*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008 125*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 126*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 127*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800 128*5113495bSYour Name 129*5113495bSYour Name 130*5113495bSYour Name 131*5113495bSYour Name 132*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008 133*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32 134*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63 135*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000 136*5113495bSYour Name 137*5113495bSYour Name 138*5113495bSYour Name 139*5113495bSYour Name 140*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 141*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 142*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 143*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff 144*5113495bSYour Name 145*5113495bSYour Name 146*5113495bSYour Name 147*5113495bSYour Name 148*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010 149*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32 150*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63 151*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000 152*5113495bSYour Name 153*5113495bSYour Name 154*5113495bSYour Name 155*5113495bSYour Name 156*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018 157*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 158*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 159*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff 160*5113495bSYour Name 161*5113495bSYour Name 162*5113495bSYour Name 163*5113495bSYour Name 164*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018 165*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32 166*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63 167*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000 168*5113495bSYour Name 169*5113495bSYour Name 170*5113495bSYour Name 171*5113495bSYour Name 172*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020 173*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 174*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 175*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff 176*5113495bSYour Name 177*5113495bSYour Name 178*5113495bSYour Name 179*5113495bSYour Name 180*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 181*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32 182*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63 183*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 184*5113495bSYour Name 185*5113495bSYour Name 186*5113495bSYour Name 187*5113495bSYour Name #endif 188