1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _REO_FLUSH_QUEUE_H_ 20 #define _REO_FLUSH_QUEUE_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_cmd_header.h" 25 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10 26 27 #define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5 28 29 30 struct reo_flush_queue { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct uniform_reo_cmd_header cmd_header; 33 uint32_t flush_desc_addr_31_0 : 32; 34 uint32_t flush_desc_addr_39_32 : 8, 35 block_desc_addr_usage_after_flush : 1, 36 block_resource_index : 2, 37 reserved_2a : 21; 38 uint32_t reserved_3a : 32; 39 uint32_t reserved_4a : 32; 40 uint32_t reserved_5a : 32; 41 uint32_t reserved_6a : 32; 42 uint32_t reserved_7a : 32; 43 uint32_t reserved_8a : 32; 44 uint32_t tlv64_padding : 32; 45 #else 46 struct uniform_reo_cmd_header cmd_header; 47 uint32_t flush_desc_addr_31_0 : 32; 48 uint32_t reserved_2a : 21, 49 block_resource_index : 2, 50 block_desc_addr_usage_after_flush : 1, 51 flush_desc_addr_39_32 : 8; 52 uint32_t reserved_3a : 32; 53 uint32_t reserved_4a : 32; 54 uint32_t reserved_5a : 32; 55 uint32_t reserved_6a : 32; 56 uint32_t reserved_7a : 32; 57 uint32_t reserved_8a : 32; 58 uint32_t tlv64_padding : 32; 59 #endif 60 }; 61 62 63 64 65 66 67 68 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 69 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 70 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 71 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 72 73 74 75 76 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 77 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 78 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 79 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 80 81 82 83 84 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 85 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 86 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 87 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 88 89 90 91 92 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000 93 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32 94 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63 95 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000 96 97 98 99 100 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008 101 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 102 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 103 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff 104 105 106 107 108 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 109 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 110 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 111 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100 112 113 114 115 116 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 117 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 118 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 119 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600 120 121 122 123 124 #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008 125 #define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 126 #define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 127 #define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800 128 129 130 131 132 #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008 133 #define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32 134 #define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63 135 #define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000 136 137 138 139 140 #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 141 #define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 142 #define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 143 #define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff 144 145 146 147 148 #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010 149 #define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32 150 #define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63 151 #define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000 152 153 154 155 156 #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018 157 #define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 158 #define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 159 #define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff 160 161 162 163 164 #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018 165 #define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32 166 #define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63 167 #define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000 168 169 170 171 172 #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020 173 #define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 174 #define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 175 #define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff 176 177 178 179 180 #define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 181 #define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32 182 #define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63 183 #define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 184 185 186 187 #endif 188