1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _REO_FLUSH_QUEUE_STATUS_H_ 20 #define _REO_FLUSH_QUEUE_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_status_header.h" 25 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26 26 27 #define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13 28 29 30 struct reo_flush_queue_status { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct uniform_reo_status_header status_header; 33 uint32_t error_detected : 1, 34 reserved_2a : 31; 35 uint32_t reserved_3a : 32; 36 uint32_t reserved_4a : 32; 37 uint32_t reserved_5a : 32; 38 uint32_t reserved_6a : 32; 39 uint32_t reserved_7a : 32; 40 uint32_t reserved_8a : 32; 41 uint32_t reserved_9a : 32; 42 uint32_t reserved_10a : 32; 43 uint32_t reserved_11a : 32; 44 uint32_t reserved_12a : 32; 45 uint32_t reserved_13a : 32; 46 uint32_t reserved_14a : 32; 47 uint32_t reserved_15a : 32; 48 uint32_t reserved_16a : 32; 49 uint32_t reserved_17a : 32; 50 uint32_t reserved_18a : 32; 51 uint32_t reserved_19a : 32; 52 uint32_t reserved_20a : 32; 53 uint32_t reserved_21a : 32; 54 uint32_t reserved_22a : 32; 55 uint32_t reserved_23a : 32; 56 uint32_t reserved_24a : 32; 57 uint32_t reserved_25a : 28, 58 looping_count : 4; 59 #else 60 struct uniform_reo_status_header status_header; 61 uint32_t reserved_2a : 31, 62 error_detected : 1; 63 uint32_t reserved_3a : 32; 64 uint32_t reserved_4a : 32; 65 uint32_t reserved_5a : 32; 66 uint32_t reserved_6a : 32; 67 uint32_t reserved_7a : 32; 68 uint32_t reserved_8a : 32; 69 uint32_t reserved_9a : 32; 70 uint32_t reserved_10a : 32; 71 uint32_t reserved_11a : 32; 72 uint32_t reserved_12a : 32; 73 uint32_t reserved_13a : 32; 74 uint32_t reserved_14a : 32; 75 uint32_t reserved_15a : 32; 76 uint32_t reserved_16a : 32; 77 uint32_t reserved_17a : 32; 78 uint32_t reserved_18a : 32; 79 uint32_t reserved_19a : 32; 80 uint32_t reserved_20a : 32; 81 uint32_t reserved_21a : 32; 82 uint32_t reserved_22a : 32; 83 uint32_t reserved_23a : 32; 84 uint32_t reserved_24a : 32; 85 uint32_t looping_count : 4, 86 reserved_25a : 28; 87 #endif 88 }; 89 90 91 92 93 94 95 96 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 97 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 98 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 99 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 100 101 102 103 104 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 105 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 106 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 107 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 108 109 110 111 112 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 113 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 114 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 115 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 116 117 118 119 120 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 121 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 122 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 123 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 124 125 126 127 128 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 129 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 130 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 131 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 132 133 134 135 136 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 137 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0 138 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0 139 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 140 141 142 143 144 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 145 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1 146 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31 147 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe 148 149 150 151 152 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 153 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32 154 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63 155 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 156 157 158 159 160 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 161 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0 162 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31 163 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 164 165 166 167 168 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 169 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32 170 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63 171 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 172 173 174 175 176 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 177 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0 178 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31 179 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 180 181 182 183 184 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 185 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32 186 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63 187 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 188 189 190 191 192 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 193 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0 194 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31 195 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 196 197 198 199 200 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 201 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32 202 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63 203 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 204 205 206 207 208 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 209 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0 210 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31 211 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 212 213 214 215 216 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 217 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32 218 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63 219 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 220 221 222 223 224 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 225 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0 226 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31 227 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 228 229 230 231 232 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 233 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32 234 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63 235 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 236 237 238 239 240 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 241 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0 242 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31 243 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 244 245 246 247 248 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 249 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32 250 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63 251 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 252 253 254 255 256 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 257 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0 258 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31 259 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 260 261 262 263 264 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 265 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32 266 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63 267 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 268 269 270 271 272 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 273 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0 274 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31 275 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 276 277 278 279 280 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 281 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32 282 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63 283 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 284 285 286 287 288 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 289 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0 290 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31 291 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 292 293 294 295 296 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 297 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32 298 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63 299 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 300 301 302 303 304 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 305 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0 306 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31 307 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 308 309 310 311 312 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 313 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32 314 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63 315 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 316 317 318 319 320 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 321 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0 322 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31 323 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 324 325 326 327 328 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 329 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32 330 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59 331 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 332 333 334 335 336 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 337 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60 338 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63 339 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 340 341 342 343 #endif 344