1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 20 #define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_status_header.h" 25 #define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26 26 27 #define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13 28 29 30 struct reo_flush_timeout_list_status { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct uniform_reo_status_header status_header; 33 uint32_t error_detected : 1, 34 timout_list_empty : 1, 35 reserved_2a : 30; 36 uint32_t release_desc_count : 16, 37 forward_buf_count : 16; 38 uint32_t reserved_4a : 32; 39 uint32_t reserved_5a : 32; 40 uint32_t reserved_6a : 32; 41 uint32_t reserved_7a : 32; 42 uint32_t reserved_8a : 32; 43 uint32_t reserved_9a : 32; 44 uint32_t reserved_10a : 32; 45 uint32_t reserved_11a : 32; 46 uint32_t reserved_12a : 32; 47 uint32_t reserved_13a : 32; 48 uint32_t reserved_14a : 32; 49 uint32_t reserved_15a : 32; 50 uint32_t reserved_16a : 32; 51 uint32_t reserved_17a : 32; 52 uint32_t reserved_18a : 32; 53 uint32_t reserved_19a : 32; 54 uint32_t reserved_20a : 32; 55 uint32_t reserved_21a : 32; 56 uint32_t reserved_22a : 32; 57 uint32_t reserved_23a : 32; 58 uint32_t reserved_24a : 32; 59 uint32_t reserved_25a : 28, 60 looping_count : 4; 61 #else 62 struct uniform_reo_status_header status_header; 63 uint32_t reserved_2a : 30, 64 timout_list_empty : 1, 65 error_detected : 1; 66 uint32_t forward_buf_count : 16, 67 release_desc_count : 16; 68 uint32_t reserved_4a : 32; 69 uint32_t reserved_5a : 32; 70 uint32_t reserved_6a : 32; 71 uint32_t reserved_7a : 32; 72 uint32_t reserved_8a : 32; 73 uint32_t reserved_9a : 32; 74 uint32_t reserved_10a : 32; 75 uint32_t reserved_11a : 32; 76 uint32_t reserved_12a : 32; 77 uint32_t reserved_13a : 32; 78 uint32_t reserved_14a : 32; 79 uint32_t reserved_15a : 32; 80 uint32_t reserved_16a : 32; 81 uint32_t reserved_17a : 32; 82 uint32_t reserved_18a : 32; 83 uint32_t reserved_19a : 32; 84 uint32_t reserved_20a : 32; 85 uint32_t reserved_21a : 32; 86 uint32_t reserved_22a : 32; 87 uint32_t reserved_23a : 32; 88 uint32_t reserved_24a : 32; 89 uint32_t looping_count : 4, 90 reserved_25a : 28; 91 #endif 92 }; 93 94 95 96 97 98 99 100 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 101 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 102 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 103 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 104 105 106 107 108 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 109 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 110 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 111 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 112 113 114 115 116 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 117 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 118 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 119 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 120 121 122 123 124 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 125 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 126 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 127 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 128 129 130 131 132 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 133 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 134 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 135 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 136 137 138 139 140 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 141 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 142 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 143 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 144 145 146 147 148 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008 149 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 150 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 151 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002 152 153 154 155 156 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 157 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 158 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 159 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc 160 161 162 163 164 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 165 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32 166 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47 167 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000 168 169 170 171 172 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 173 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48 174 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63 175 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000 176 177 178 179 180 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 181 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 182 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 183 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 184 185 186 187 188 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 189 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32 190 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63 191 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000 192 193 194 195 196 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 197 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 198 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 199 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 200 201 202 203 204 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 205 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32 206 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63 207 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000 208 209 210 211 212 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 213 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 214 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 215 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 216 217 218 219 220 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 221 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32 222 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63 223 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000 224 225 226 227 228 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 229 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 230 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 231 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 232 233 234 235 236 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 237 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32 238 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63 239 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000 240 241 242 243 244 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 245 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 246 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 247 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 248 249 250 251 252 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 253 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32 254 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63 255 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000 256 257 258 259 260 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 261 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 262 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 263 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 264 265 266 267 268 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 269 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32 270 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63 271 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000 272 273 274 275 276 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 277 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 278 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 279 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 280 281 282 283 284 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 285 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32 286 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63 287 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000 288 289 290 291 292 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 293 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 294 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 295 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 296 297 298 299 300 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 301 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32 302 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63 303 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000 304 305 306 307 308 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 309 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 310 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 311 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 312 313 314 315 316 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 317 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32 318 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63 319 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000 320 321 322 323 324 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 325 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 326 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 327 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 328 329 330 331 332 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 333 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32 334 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63 335 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000 336 337 338 339 340 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 341 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 342 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 343 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 344 345 346 347 348 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 349 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32 350 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59 351 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 352 353 354 355 356 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 357 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60 358 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63 359 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 360 361 362 363 #endif 364