1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _REO_GET_QUEUE_STATS_H_ 20 #define _REO_GET_QUEUE_STATS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_cmd_header.h" 25 #define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10 26 27 #define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5 28 29 30 struct reo_get_queue_stats { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct uniform_reo_cmd_header cmd_header; 33 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 34 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 35 clear_stats : 1, 36 reserved_2a : 23; 37 uint32_t reserved_3a : 32; 38 uint32_t reserved_4a : 32; 39 uint32_t reserved_5a : 32; 40 uint32_t reserved_6a : 32; 41 uint32_t reserved_7a : 32; 42 uint32_t reserved_8a : 32; 43 uint32_t tlv64_padding : 32; 44 #else 45 struct uniform_reo_cmd_header cmd_header; 46 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 47 uint32_t reserved_2a : 23, 48 clear_stats : 1, 49 rx_reo_queue_desc_addr_39_32 : 8; 50 uint32_t reserved_3a : 32; 51 uint32_t reserved_4a : 32; 52 uint32_t reserved_5a : 32; 53 uint32_t reserved_6a : 32; 54 uint32_t reserved_7a : 32; 55 uint32_t reserved_8a : 32; 56 uint32_t tlv64_padding : 32; 57 #endif 58 }; 59 60 61 62 63 64 65 66 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 67 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0 68 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15 69 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 70 71 72 73 74 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 75 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 76 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 77 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 78 79 80 81 82 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 83 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17 84 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31 85 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 86 87 88 89 90 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 91 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 92 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 93 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 94 95 96 97 98 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 99 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 100 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 101 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff 102 103 104 105 106 #define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x0000000000000008 107 #define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8 108 #define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8 109 #define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x0000000000000100 110 111 112 113 114 #define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x0000000000000008 115 #define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9 116 #define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31 117 #define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0x00000000fffffe00 118 119 120 121 122 #define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000000000008 123 #define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 32 124 #define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 63 125 #define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff00000000 126 127 128 129 130 #define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x0000000000000010 131 #define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0 132 #define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31 133 #define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0x00000000ffffffff 134 135 136 137 138 #define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x0000000000000010 139 #define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 32 140 #define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 63 141 #define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff00000000 142 143 144 145 146 #define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x0000000000000018 147 #define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0 148 #define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31 149 #define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0x00000000ffffffff 150 151 152 153 154 #define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000000000000018 155 #define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 32 156 #define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 63 157 #define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff00000000 158 159 160 161 162 #define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x0000000000000020 163 #define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0 164 #define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31 165 #define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0x00000000ffffffff 166 167 168 169 170 #define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET 0x0000000000000020 171 #define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB 32 172 #define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB 63 173 #define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK 0xffffffff00000000 174 175 176 177 #endif 178