1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _REO_UNBLOCK_CACHE_STATUS_H_ 20 #define _REO_UNBLOCK_CACHE_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_status_header.h" 25 #define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26 26 27 #define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13 28 29 30 struct reo_unblock_cache_status { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct uniform_reo_status_header status_header; 33 uint32_t error_detected : 1, 34 unblock_type : 1, 35 reserved_2a : 30; 36 uint32_t reserved_3a : 32; 37 uint32_t reserved_4a : 32; 38 uint32_t reserved_5a : 32; 39 uint32_t reserved_6a : 32; 40 uint32_t reserved_7a : 32; 41 uint32_t reserved_8a : 32; 42 uint32_t reserved_9a : 32; 43 uint32_t reserved_10a : 32; 44 uint32_t reserved_11a : 32; 45 uint32_t reserved_12a : 32; 46 uint32_t reserved_13a : 32; 47 uint32_t reserved_14a : 32; 48 uint32_t reserved_15a : 32; 49 uint32_t reserved_16a : 32; 50 uint32_t reserved_17a : 32; 51 uint32_t reserved_18a : 32; 52 uint32_t reserved_19a : 32; 53 uint32_t reserved_20a : 32; 54 uint32_t reserved_21a : 32; 55 uint32_t reserved_22a : 32; 56 uint32_t reserved_23a : 32; 57 uint32_t reserved_24a : 32; 58 uint32_t reserved_25a : 28, 59 looping_count : 4; 60 #else 61 struct uniform_reo_status_header status_header; 62 uint32_t reserved_2a : 30, 63 unblock_type : 1, 64 error_detected : 1; 65 uint32_t reserved_3a : 32; 66 uint32_t reserved_4a : 32; 67 uint32_t reserved_5a : 32; 68 uint32_t reserved_6a : 32; 69 uint32_t reserved_7a : 32; 70 uint32_t reserved_8a : 32; 71 uint32_t reserved_9a : 32; 72 uint32_t reserved_10a : 32; 73 uint32_t reserved_11a : 32; 74 uint32_t reserved_12a : 32; 75 uint32_t reserved_13a : 32; 76 uint32_t reserved_14a : 32; 77 uint32_t reserved_15a : 32; 78 uint32_t reserved_16a : 32; 79 uint32_t reserved_17a : 32; 80 uint32_t reserved_18a : 32; 81 uint32_t reserved_19a : 32; 82 uint32_t reserved_20a : 32; 83 uint32_t reserved_21a : 32; 84 uint32_t reserved_22a : 32; 85 uint32_t reserved_23a : 32; 86 uint32_t reserved_24a : 32; 87 uint32_t looping_count : 4, 88 reserved_25a : 28; 89 #endif 90 }; 91 92 93 94 95 96 97 98 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 99 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 100 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 101 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 102 103 104 105 106 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 107 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 108 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 109 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 110 111 112 113 114 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 115 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 116 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 117 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 118 119 120 121 122 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 123 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 124 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 125 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 126 127 128 129 130 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 131 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 132 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 133 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 134 135 136 137 138 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 139 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0 140 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0 141 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 142 143 144 145 146 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000000000008 147 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1 148 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1 149 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x0000000000000002 150 151 152 153 154 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 155 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2 156 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31 157 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0x00000000fffffffc 158 159 160 161 162 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 163 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 32 164 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 63 165 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 166 167 168 169 170 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 171 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0 172 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31 173 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 174 175 176 177 178 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 179 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 32 180 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 63 181 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 182 183 184 185 186 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 187 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0 188 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31 189 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 190 191 192 193 194 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 195 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 32 196 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 63 197 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 198 199 200 201 202 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 203 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0 204 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31 205 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 206 207 208 209 210 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 211 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 32 212 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 63 213 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 214 215 216 217 218 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 219 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0 220 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31 221 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 222 223 224 225 226 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 227 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 32 228 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 63 229 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 230 231 232 233 234 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 235 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0 236 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31 237 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 238 239 240 241 242 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 243 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 32 244 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 63 245 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 246 247 248 249 250 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 251 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0 252 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31 253 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 254 255 256 257 258 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 259 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 32 260 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 63 261 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 262 263 264 265 266 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 267 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0 268 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31 269 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 270 271 272 273 274 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 275 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 32 276 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 63 277 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 278 279 280 281 282 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 283 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0 284 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31 285 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 286 287 288 289 290 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 291 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 32 292 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 63 293 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 294 295 296 297 298 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 299 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0 300 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31 301 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 302 303 304 305 306 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 307 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 32 308 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 63 309 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 310 311 312 313 314 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 315 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0 316 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31 317 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 318 319 320 321 322 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 323 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 32 324 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 63 325 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 326 327 328 329 330 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 331 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0 332 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31 333 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 334 335 336 337 338 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 339 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 32 340 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 59 341 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 342 343 344 345 346 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 347 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 60 348 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 63 349 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 350 351 352 353 #endif 354