1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _REO_UPDATE_RX_REO_QUEUE_H_ 20 #define _REO_UPDATE_RX_REO_QUEUE_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_cmd_header.h" 25 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10 26 27 #define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5 28 29 30 struct reo_update_rx_reo_queue { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct uniform_reo_cmd_header cmd_header; 33 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 34 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 35 update_receive_queue_number : 1, 36 update_vld : 1, 37 update_associated_link_descriptor_counter : 1, 38 update_disable_duplicate_detection : 1, 39 update_soft_reorder_enable : 1, 40 update_ac : 1, 41 update_bar : 1, 42 update_rty : 1, 43 update_chk_2k_mode : 1, 44 update_oor_mode : 1, 45 update_ba_window_size : 1, 46 update_pn_check_needed : 1, 47 update_pn_shall_be_even : 1, 48 update_pn_shall_be_uneven : 1, 49 update_pn_handling_enable : 1, 50 update_pn_size : 1, 51 update_ignore_ampdu_flag : 1, 52 update_svld : 1, 53 update_ssn : 1, 54 update_seq_2k_error_detected_flag : 1, 55 update_pn_error_detected_flag : 1, 56 update_pn_valid : 1, 57 update_pn : 1, 58 clear_stat_counters : 1; 59 uint32_t receive_queue_number : 16, 60 vld : 1, 61 associated_link_descriptor_counter : 2, 62 disable_duplicate_detection : 1, 63 soft_reorder_enable : 1, 64 ac : 2, 65 bar : 1, 66 rty : 1, 67 chk_2k_mode : 1, 68 oor_mode : 1, 69 pn_check_needed : 1, 70 pn_shall_be_even : 1, 71 pn_shall_be_uneven : 1, 72 pn_handling_enable : 1, 73 ignore_ampdu_flag : 1; 74 uint32_t ba_window_size : 10, 75 pn_size : 2, 76 svld : 1, 77 ssn : 12, 78 seq_2k_error_detected_flag : 1, 79 pn_error_detected_flag : 1, 80 pn_valid : 1, 81 flush_from_cache : 1, 82 reserved_4a : 3; 83 uint32_t pn_31_0 : 32; 84 uint32_t pn_63_32 : 32; 85 uint32_t pn_95_64 : 32; 86 uint32_t pn_127_96 : 32; 87 uint32_t tlv64_padding : 32; 88 #else 89 struct uniform_reo_cmd_header cmd_header; 90 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 91 uint32_t clear_stat_counters : 1, 92 update_pn : 1, 93 update_pn_valid : 1, 94 update_pn_error_detected_flag : 1, 95 update_seq_2k_error_detected_flag : 1, 96 update_ssn : 1, 97 update_svld : 1, 98 update_ignore_ampdu_flag : 1, 99 update_pn_size : 1, 100 update_pn_handling_enable : 1, 101 update_pn_shall_be_uneven : 1, 102 update_pn_shall_be_even : 1, 103 update_pn_check_needed : 1, 104 update_ba_window_size : 1, 105 update_oor_mode : 1, 106 update_chk_2k_mode : 1, 107 update_rty : 1, 108 update_bar : 1, 109 update_ac : 1, 110 update_soft_reorder_enable : 1, 111 update_disable_duplicate_detection : 1, 112 update_associated_link_descriptor_counter : 1, 113 update_vld : 1, 114 update_receive_queue_number : 1, 115 rx_reo_queue_desc_addr_39_32 : 8; 116 uint32_t ignore_ampdu_flag : 1, 117 pn_handling_enable : 1, 118 pn_shall_be_uneven : 1, 119 pn_shall_be_even : 1, 120 pn_check_needed : 1, 121 oor_mode : 1, 122 chk_2k_mode : 1, 123 rty : 1, 124 bar : 1, 125 ac : 2, 126 soft_reorder_enable : 1, 127 disable_duplicate_detection : 1, 128 associated_link_descriptor_counter : 2, 129 vld : 1, 130 receive_queue_number : 16; 131 uint32_t reserved_4a : 3, 132 flush_from_cache : 1, 133 pn_valid : 1, 134 pn_error_detected_flag : 1, 135 seq_2k_error_detected_flag : 1, 136 ssn : 12, 137 svld : 1, 138 pn_size : 2, 139 ba_window_size : 10; 140 uint32_t pn_31_0 : 32; 141 uint32_t pn_63_32 : 32; 142 uint32_t pn_95_64 : 32; 143 uint32_t pn_127_96 : 32; 144 uint32_t tlv64_padding : 32; 145 #endif 146 }; 147 148 149 150 151 152 153 154 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 155 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 156 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 157 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 158 159 160 161 162 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 163 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 164 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 165 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 166 167 168 169 170 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 171 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 172 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 173 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 174 175 176 177 178 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 179 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 180 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 181 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 182 183 184 185 186 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 187 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 188 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 189 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff 190 191 192 193 194 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 195 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 196 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 197 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100 198 199 200 201 202 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008 203 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 204 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 205 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200 206 207 208 209 210 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 211 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 212 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 213 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400 214 215 216 217 218 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 219 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 220 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 221 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800 222 223 224 225 226 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 227 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 228 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 229 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000 230 231 232 233 234 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008 235 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 236 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 237 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000 238 239 240 241 242 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008 243 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 244 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 245 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000 246 247 248 249 250 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008 251 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 252 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 253 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000 254 255 256 257 258 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008 259 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 260 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 261 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000 262 263 264 265 266 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008 267 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 268 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 269 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000 270 271 272 273 274 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008 275 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 276 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 277 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000 278 279 280 281 282 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 283 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 284 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 285 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000 286 287 288 289 290 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 291 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 292 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 293 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000 294 295 296 297 298 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 299 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 300 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 301 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000 302 303 304 305 306 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 307 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 308 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 309 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000 310 311 312 313 314 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008 315 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 316 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 317 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000 318 319 320 321 322 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 323 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 324 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 325 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000 326 327 328 329 330 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008 331 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 332 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 333 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000 334 335 336 337 338 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008 339 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 340 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 341 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000 342 343 344 345 346 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 347 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 348 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 349 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000 350 351 352 353 354 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 355 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 356 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 357 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000 358 359 360 361 362 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008 363 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 364 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 365 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000 366 367 368 369 370 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008 371 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 372 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 373 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000 374 375 376 377 378 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008 379 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 380 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 381 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000 382 383 384 385 386 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 387 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32 388 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47 389 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000 390 391 392 393 394 #define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008 395 #define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48 396 #define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48 397 #define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000 398 399 400 401 402 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 403 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49 404 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50 405 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000 406 407 408 409 410 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 411 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51 412 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51 413 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000 414 415 416 417 418 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 419 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52 420 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52 421 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000 422 423 424 425 426 #define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008 427 #define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53 428 #define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54 429 #define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000 430 431 432 433 434 #define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008 435 #define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55 436 #define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55 437 #define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000 438 439 440 441 442 #define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008 443 #define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56 444 #define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56 445 #define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000 446 447 448 449 450 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008 451 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57 452 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57 453 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000 454 455 456 457 458 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008 459 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58 460 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58 461 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000 462 463 464 465 466 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 467 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59 468 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59 469 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000 470 471 472 473 474 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 475 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60 476 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60 477 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000 478 479 480 481 482 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 483 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61 484 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61 485 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000 486 487 488 489 490 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 491 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62 492 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62 493 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000 494 495 496 497 498 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 499 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63 500 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63 501 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000 502 503 504 505 506 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010 507 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 508 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 509 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff 510 511 512 513 514 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010 515 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 516 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 517 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00 518 519 520 521 522 #define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010 523 #define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 524 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 525 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000 526 527 528 529 530 #define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010 531 #define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 532 #define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 533 #define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000 534 535 536 537 538 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 539 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 540 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 541 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000 542 543 544 545 546 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 547 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 548 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 549 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000 550 551 552 553 554 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010 555 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 556 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 557 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000 558 559 560 561 562 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010 563 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 564 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 565 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000 566 567 568 569 570 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 571 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 572 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 573 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000 574 575 576 577 578 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010 579 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32 580 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63 581 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000 582 583 584 585 586 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018 587 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 588 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 589 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff 590 591 592 593 594 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018 595 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32 596 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63 597 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000 598 599 600 601 602 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020 603 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 604 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 605 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff 606 607 608 609 610 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 611 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32 612 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63 613 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 614 615 616 617 #endif 618