1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 20 #define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_status_header.h" 25 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26 26 27 #define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13 28 29 30 struct reo_update_rx_reo_queue_status { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct uniform_reo_status_header status_header; 33 uint32_t reserved_2a : 32; 34 uint32_t reserved_3a : 32; 35 uint32_t reserved_4a : 32; 36 uint32_t reserved_5a : 32; 37 uint32_t reserved_6a : 32; 38 uint32_t reserved_7a : 32; 39 uint32_t reserved_8a : 32; 40 uint32_t reserved_9a : 32; 41 uint32_t reserved_10a : 32; 42 uint32_t reserved_11a : 32; 43 uint32_t reserved_12a : 32; 44 uint32_t reserved_13a : 32; 45 uint32_t reserved_14a : 32; 46 uint32_t reserved_15a : 32; 47 uint32_t reserved_16a : 32; 48 uint32_t reserved_17a : 32; 49 uint32_t reserved_18a : 32; 50 uint32_t reserved_19a : 32; 51 uint32_t reserved_20a : 32; 52 uint32_t reserved_21a : 32; 53 uint32_t reserved_22a : 32; 54 uint32_t reserved_23a : 32; 55 uint32_t reserved_24a : 32; 56 uint32_t reserved_25a : 28, 57 looping_count : 4; 58 #else 59 struct uniform_reo_status_header status_header; 60 uint32_t reserved_2a : 32; 61 uint32_t reserved_3a : 32; 62 uint32_t reserved_4a : 32; 63 uint32_t reserved_5a : 32; 64 uint32_t reserved_6a : 32; 65 uint32_t reserved_7a : 32; 66 uint32_t reserved_8a : 32; 67 uint32_t reserved_9a : 32; 68 uint32_t reserved_10a : 32; 69 uint32_t reserved_11a : 32; 70 uint32_t reserved_12a : 32; 71 uint32_t reserved_13a : 32; 72 uint32_t reserved_14a : 32; 73 uint32_t reserved_15a : 32; 74 uint32_t reserved_16a : 32; 75 uint32_t reserved_17a : 32; 76 uint32_t reserved_18a : 32; 77 uint32_t reserved_19a : 32; 78 uint32_t reserved_20a : 32; 79 uint32_t reserved_21a : 32; 80 uint32_t reserved_22a : 32; 81 uint32_t reserved_23a : 32; 82 uint32_t reserved_24a : 32; 83 uint32_t looping_count : 4, 84 reserved_25a : 28; 85 #endif 86 }; 87 88 89 90 91 92 93 94 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 95 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 96 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 97 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 98 99 100 101 102 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 103 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 104 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 105 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 106 107 108 109 110 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 111 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 112 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 113 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 114 115 116 117 118 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 119 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 120 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 121 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 122 123 124 125 126 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 127 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 128 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 129 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 130 131 132 133 134 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 135 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0 136 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31 137 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000ffffffff 138 139 140 141 142 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 143 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 32 144 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 63 145 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 146 147 148 149 150 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 151 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0 152 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31 153 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 154 155 156 157 158 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 159 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 32 160 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 63 161 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 162 163 164 165 166 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 167 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0 168 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31 169 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 170 171 172 173 174 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 175 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 32 176 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 63 177 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 178 179 180 181 182 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 183 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0 184 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31 185 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 186 187 188 189 190 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 191 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 32 192 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 63 193 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 194 195 196 197 198 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 199 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0 200 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31 201 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 202 203 204 205 206 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 207 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 32 208 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 63 209 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 210 211 212 213 214 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 215 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0 216 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31 217 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 218 219 220 221 222 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 223 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 32 224 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 63 225 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 226 227 228 229 230 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 231 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0 232 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31 233 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 234 235 236 237 238 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 239 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 32 240 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 63 241 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 242 243 244 245 246 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 247 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0 248 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31 249 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 250 251 252 253 254 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 255 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 32 256 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 63 257 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 258 259 260 261 262 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 263 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0 264 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31 265 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 266 267 268 269 270 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 271 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 32 272 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 63 273 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 274 275 276 277 278 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 279 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0 280 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31 281 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 282 283 284 285 286 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 287 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 32 288 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 63 289 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 290 291 292 293 294 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 295 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0 296 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31 297 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 298 299 300 301 302 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 303 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 32 304 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 63 305 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 306 307 308 309 310 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 311 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0 312 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31 313 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 314 315 316 317 318 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 319 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 32 320 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 59 321 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 322 323 324 325 326 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 327 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 60 328 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 63 329 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 330 331 332 333 #endif 334