1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RESPONSE_END_STATUS_H_ 20 #define _RESPONSE_END_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "phytx_abort_request_info.h" 25 #define NUM_OF_DWORDS_RESPONSE_END_STATUS 22 26 27 #define NUM_OF_QWORDS_RESPONSE_END_STATUS 11 28 29 30 struct response_end_status { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t coex_bt_tx_while_wlan_tx : 1, 33 coex_wan_tx_while_wlan_tx : 1, 34 coex_wlan_tx_while_wlan_tx : 1, 35 global_data_underflow_warning : 1, 36 response_transmit_status : 4, 37 phytx_pkt_end_info_valid : 1, 38 phytx_abort_request_info_valid : 1, 39 generated_response : 3, 40 mba_user_count : 7, 41 mba_fake_bitmap_count : 7, 42 coex_based_tx_bw : 3, 43 trig_response_related : 1, 44 dpdtrain_done : 1; 45 struct phytx_abort_request_info phytx_abort_request_info_details; 46 uint16_t cbf_segment_request_mask : 8, 47 cbf_segment_sent_mask : 8; 48 uint32_t underflow_mpdu_count : 9, 49 data_underflow_warning : 2, 50 phy_tx_gain_setting : 8, 51 timing_status : 2, 52 only_null_delim_sent : 1, 53 brp_info_valid : 1, 54 reserved_2a : 9; 55 uint32_t mu_response_bitmap_31_0 : 32; 56 uint32_t mu_response_bitmap_36_32 : 5, 57 reserved_4a : 11, 58 transmit_delay : 16; 59 uint32_t start_of_frame_timestamp_15_0 : 16, 60 start_of_frame_timestamp_31_16 : 16; 61 uint32_t end_of_frame_timestamp_15_0 : 16, 62 end_of_frame_timestamp_31_16 : 16; 63 uint32_t tx_group_delay : 12, 64 reserved_7a : 4, 65 tpc_dbg_info_cmn_15_0 : 16; 66 uint32_t tpc_dbg_info_31_16 : 16, 67 tpc_dbg_info_47_32 : 16; 68 uint32_t tpc_dbg_info_chn1_15_0 : 16, 69 tpc_dbg_info_chn1_31_16 : 16; 70 uint32_t tpc_dbg_info_chn1_47_32 : 16, 71 tpc_dbg_info_chn1_63_48 : 16; 72 uint32_t tpc_dbg_info_chn1_79_64 : 16, 73 tpc_dbg_info_chn2_15_0 : 16; 74 uint32_t tpc_dbg_info_chn2_31_16 : 16, 75 tpc_dbg_info_chn2_47_32 : 16; 76 uint32_t tpc_dbg_info_chn2_63_48 : 16, 77 tpc_dbg_info_chn2_79_64 : 16; 78 uint32_t phytx_tx_end_sw_info_15_0 : 16, 79 phytx_tx_end_sw_info_31_16 : 16; 80 uint32_t phytx_tx_end_sw_info_47_32 : 16, 81 phytx_tx_end_sw_info_63_48 : 16; 82 uint32_t addr1_31_0 : 32; 83 uint32_t addr1_47_32 : 16, 84 addr2_15_0 : 16; 85 uint32_t addr2_47_16 : 32; 86 uint32_t addr3_31_0 : 32; 87 uint32_t addr3_47_32 : 16, 88 ranging : 1, 89 secure : 1, 90 ranging_ftm_frame_sent : 1, 91 reserved_20a : 13; 92 uint32_t tlv64_padding : 32; 93 #else 94 uint32_t dpdtrain_done : 1, 95 trig_response_related : 1, 96 coex_based_tx_bw : 3, 97 mba_fake_bitmap_count : 7, 98 mba_user_count : 7, 99 generated_response : 3, 100 phytx_abort_request_info_valid : 1, 101 phytx_pkt_end_info_valid : 1, 102 response_transmit_status : 4, 103 global_data_underflow_warning : 1, 104 coex_wlan_tx_while_wlan_tx : 1, 105 coex_wan_tx_while_wlan_tx : 1, 106 coex_bt_tx_while_wlan_tx : 1; 107 uint32_t cbf_segment_sent_mask : 8, 108 cbf_segment_request_mask : 8; 109 struct phytx_abort_request_info phytx_abort_request_info_details; 110 uint32_t reserved_2a : 9, 111 brp_info_valid : 1, 112 only_null_delim_sent : 1, 113 timing_status : 2, 114 phy_tx_gain_setting : 8, 115 data_underflow_warning : 2, 116 underflow_mpdu_count : 9; 117 uint32_t mu_response_bitmap_31_0 : 32; 118 uint32_t transmit_delay : 16, 119 reserved_4a : 11, 120 mu_response_bitmap_36_32 : 5; 121 uint32_t start_of_frame_timestamp_31_16 : 16, 122 start_of_frame_timestamp_15_0 : 16; 123 uint32_t end_of_frame_timestamp_31_16 : 16, 124 end_of_frame_timestamp_15_0 : 16; 125 uint32_t tpc_dbg_info_cmn_15_0 : 16, 126 reserved_7a : 4, 127 tx_group_delay : 12; 128 uint32_t tpc_dbg_info_47_32 : 16, 129 tpc_dbg_info_31_16 : 16; 130 uint32_t tpc_dbg_info_chn1_31_16 : 16, 131 tpc_dbg_info_chn1_15_0 : 16; 132 uint32_t tpc_dbg_info_chn1_63_48 : 16, 133 tpc_dbg_info_chn1_47_32 : 16; 134 uint32_t tpc_dbg_info_chn2_15_0 : 16, 135 tpc_dbg_info_chn1_79_64 : 16; 136 uint32_t tpc_dbg_info_chn2_47_32 : 16, 137 tpc_dbg_info_chn2_31_16 : 16; 138 uint32_t tpc_dbg_info_chn2_79_64 : 16, 139 tpc_dbg_info_chn2_63_48 : 16; 140 uint32_t phytx_tx_end_sw_info_31_16 : 16, 141 phytx_tx_end_sw_info_15_0 : 16; 142 uint32_t phytx_tx_end_sw_info_63_48 : 16, 143 phytx_tx_end_sw_info_47_32 : 16; 144 uint32_t addr1_31_0 : 32; 145 uint32_t addr2_15_0 : 16, 146 addr1_47_32 : 16; 147 uint32_t addr2_47_16 : 32; 148 uint32_t addr3_31_0 : 32; 149 uint32_t reserved_20a : 13, 150 ranging_ftm_frame_sent : 1, 151 secure : 1, 152 ranging : 1, 153 addr3_47_32 : 16; 154 uint32_t tlv64_padding : 32; 155 #endif 156 }; 157 158 159 160 161 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 162 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 163 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 164 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 165 166 167 168 169 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 170 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 171 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 172 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000002 173 174 175 176 177 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 178 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 179 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 180 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 181 182 183 184 185 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 186 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 187 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 188 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 189 190 191 192 193 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 194 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 195 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 196 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 197 198 199 200 201 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 202 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 203 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 204 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 205 206 207 208 209 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 210 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 211 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 212 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 213 214 215 216 217 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 218 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 219 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 220 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 221 222 223 224 225 #define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 226 #define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 227 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 228 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 229 230 231 232 233 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 234 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 235 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 236 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 237 238 239 240 241 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 242 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 243 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 244 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 245 246 247 248 249 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 250 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 251 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 252 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 253 254 255 256 257 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_OFFSET 0x0000000000000000 258 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_LSB 31 259 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_MSB 31 260 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_MASK 0x0000000080000000 261 262 263 264 265 266 267 268 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 269 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 270 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 271 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 272 273 274 275 276 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 277 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 278 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 279 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 280 281 282 283 284 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 285 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 286 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 287 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 288 289 290 291 292 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 293 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 294 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 295 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 296 297 298 299 300 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 301 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 302 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 303 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 304 305 306 307 308 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 309 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 310 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 311 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff 312 313 314 315 316 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 317 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 318 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 319 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 320 321 322 323 324 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_OFFSET 0x0000000000000008 325 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_LSB 11 326 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MSB 18 327 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MASK 0x000000000007f800 328 329 330 331 332 #define RESPONSE_END_STATUS_TIMING_STATUS_OFFSET 0x0000000000000008 333 #define RESPONSE_END_STATUS_TIMING_STATUS_LSB 19 334 #define RESPONSE_END_STATUS_TIMING_STATUS_MSB 20 335 #define RESPONSE_END_STATUS_TIMING_STATUS_MASK 0x0000000000180000 336 337 338 339 340 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 341 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 342 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 343 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 344 345 346 347 348 #define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 349 #define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 350 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 351 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 352 353 354 355 356 #define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 357 #define RESPONSE_END_STATUS_RESERVED_2A_LSB 23 358 #define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 359 #define RESPONSE_END_STATUS_RESERVED_2A_MASK 0x00000000ff800000 360 361 362 363 364 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 365 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 366 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 367 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 368 369 370 371 372 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 373 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 374 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 375 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f 376 377 378 379 380 #define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 381 #define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 382 #define RESPONSE_END_STATUS_RESERVED_4A_MSB 15 383 #define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x000000000000ffe0 384 385 386 387 388 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_OFFSET 0x0000000000000010 389 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_LSB 16 390 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_MSB 31 391 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_MASK 0x00000000ffff0000 392 393 394 395 396 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000010 397 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_LSB 32 398 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MSB 47 399 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 400 401 402 403 404 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000010 405 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_LSB 48 406 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MSB 63 407 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 408 409 410 411 412 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000018 413 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 414 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 415 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 416 417 418 419 420 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000018 421 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_LSB 16 422 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MSB 31 423 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 424 425 426 427 428 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_OFFSET 0x0000000000000018 429 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_LSB 32 430 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_MSB 43 431 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_MASK 0x00000fff00000000 432 433 434 435 436 #define RESPONSE_END_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 437 #define RESPONSE_END_STATUS_RESERVED_7A_LSB 44 438 #define RESPONSE_END_STATUS_RESERVED_7A_MSB 47 439 #define RESPONSE_END_STATUS_RESERVED_7A_MASK 0x0000f00000000000 440 441 442 443 444 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000018 445 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_LSB 48 446 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MSB 63 447 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 448 449 450 451 452 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_OFFSET 0x0000000000000020 453 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_LSB 0 454 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MSB 15 455 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MASK 0x000000000000ffff 456 457 458 459 460 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000020 461 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_LSB 16 462 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MSB 31 463 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 464 465 466 467 468 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000020 469 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_LSB 32 470 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MSB 47 471 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 472 473 474 475 476 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000020 477 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_LSB 48 478 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MSB 63 479 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 480 481 482 483 484 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000028 485 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_LSB 0 486 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MSB 15 487 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff 488 489 490 491 492 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000028 493 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_LSB 16 494 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MSB 31 495 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 496 497 498 499 500 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000028 501 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_LSB 32 502 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MSB 47 503 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 504 505 506 507 508 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000028 509 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_LSB 48 510 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MSB 63 511 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 512 513 514 515 516 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000030 517 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_LSB 0 518 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MSB 15 519 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff 520 521 522 523 524 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000030 525 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_LSB 16 526 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MSB 31 527 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 528 529 530 531 532 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000030 533 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_LSB 32 534 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MSB 47 535 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 536 537 538 539 540 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000030 541 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_LSB 48 542 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MSB 63 543 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 544 545 546 547 548 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000038 549 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_LSB 0 550 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MSB 15 551 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 552 553 554 555 556 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000038 557 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_LSB 16 558 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MSB 31 559 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 560 561 562 563 564 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000038 565 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_LSB 32 566 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MSB 47 567 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 568 569 570 571 572 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000038 573 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_LSB 48 574 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MSB 63 575 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 576 577 578 579 580 #define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000040 581 #define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 582 #define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 583 #define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0x00000000ffffffff 584 585 586 587 588 #define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000040 589 #define RESPONSE_END_STATUS_ADDR1_47_32_LSB 32 590 #define RESPONSE_END_STATUS_ADDR1_47_32_MSB 47 591 #define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff00000000 592 593 594 595 596 #define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000040 597 #define RESPONSE_END_STATUS_ADDR2_15_0_LSB 48 598 #define RESPONSE_END_STATUS_ADDR2_15_0_MSB 63 599 #define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff000000000000 600 601 602 603 604 #define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000048 605 #define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 606 #define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 607 #define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0x00000000ffffffff 608 609 610 611 612 #define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000048 613 #define RESPONSE_END_STATUS_ADDR3_31_0_LSB 32 614 #define RESPONSE_END_STATUS_ADDR3_31_0_MSB 63 615 #define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff00000000 616 617 618 619 620 #define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000050 621 #define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 622 #define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 623 #define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x000000000000ffff 624 625 626 627 628 #define RESPONSE_END_STATUS_RANGING_OFFSET 0x0000000000000050 629 #define RESPONSE_END_STATUS_RANGING_LSB 16 630 #define RESPONSE_END_STATUS_RANGING_MSB 16 631 #define RESPONSE_END_STATUS_RANGING_MASK 0x0000000000010000 632 633 634 635 636 #define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000050 637 #define RESPONSE_END_STATUS_SECURE_LSB 17 638 #define RESPONSE_END_STATUS_SECURE_MSB 17 639 #define RESPONSE_END_STATUS_SECURE_MASK 0x0000000000020000 640 641 642 643 644 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 645 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 646 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 647 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x0000000000040000 648 649 650 651 652 #define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 653 #define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 654 #define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 655 #define RESPONSE_END_STATUS_RESERVED_20A_MASK 0x00000000fff80000 656 657 658 659 660 #define RESPONSE_END_STATUS_TLV64_PADDING_OFFSET 0x0000000000000050 661 #define RESPONSE_END_STATUS_TLV64_PADDING_LSB 32 662 #define RESPONSE_END_STATUS_TLV64_PADDING_MSB 63 663 #define RESPONSE_END_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 664 665 666 667 #endif 668