1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_ATTENTION_H_ 20 #define _RX_ATTENTION_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RX_ATTENTION 4 25 26 #define NUM_OF_QWORDS_RX_ATTENTION 2 27 28 29 struct rx_attention { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t rxpcu_mpdu_filter_in_category : 2, 32 sw_frame_group_id : 7, 33 reserved_0 : 7, 34 phy_ppdu_id : 16; 35 uint32_t first_mpdu : 1, 36 reserved_1a : 1, 37 mcast_bcast : 1, 38 ast_index_not_found : 1, 39 ast_index_timeout : 1, 40 power_mgmt : 1, 41 non_qos : 1, 42 null_data : 1, 43 mgmt_type : 1, 44 ctrl_type : 1, 45 more_data : 1, 46 eosp : 1, 47 a_msdu_error : 1, 48 fragment_flag : 1, 49 order : 1, 50 cce_match : 1, 51 overflow_err : 1, 52 msdu_length_err : 1, 53 tcp_udp_chksum_fail : 1, 54 ip_chksum_fail : 1, 55 sa_idx_invalid : 1, 56 da_idx_invalid : 1, 57 reserved_1b : 1, 58 rx_in_tx_decrypt_byp : 1, 59 encrypt_required : 1, 60 directed : 1, 61 buffer_fragment : 1, 62 mpdu_length_err : 1, 63 tkip_mic_err : 1, 64 decrypt_err : 1, 65 unencrypted_frame_err : 1, 66 fcs_err : 1; 67 uint32_t flow_idx_timeout : 1, 68 flow_idx_invalid : 1, 69 wifi_parser_error : 1, 70 amsdu_parser_error : 1, 71 sa_idx_timeout : 1, 72 da_idx_timeout : 1, 73 msdu_limit_error : 1, 74 da_is_valid : 1, 75 da_is_mcbc : 1, 76 sa_is_valid : 1, 77 decrypt_status_code : 3, 78 rx_bitmap_not_updated : 1, 79 reserved_2 : 17, 80 msdu_done : 1; 81 uint32_t tlv64_padding : 32; 82 #else 83 uint32_t phy_ppdu_id : 16, 84 reserved_0 : 7, 85 sw_frame_group_id : 7, 86 rxpcu_mpdu_filter_in_category : 2; 87 uint32_t fcs_err : 1, 88 unencrypted_frame_err : 1, 89 decrypt_err : 1, 90 tkip_mic_err : 1, 91 mpdu_length_err : 1, 92 buffer_fragment : 1, 93 directed : 1, 94 encrypt_required : 1, 95 rx_in_tx_decrypt_byp : 1, 96 reserved_1b : 1, 97 da_idx_invalid : 1, 98 sa_idx_invalid : 1, 99 ip_chksum_fail : 1, 100 tcp_udp_chksum_fail : 1, 101 msdu_length_err : 1, 102 overflow_err : 1, 103 cce_match : 1, 104 order : 1, 105 fragment_flag : 1, 106 a_msdu_error : 1, 107 eosp : 1, 108 more_data : 1, 109 ctrl_type : 1, 110 mgmt_type : 1, 111 null_data : 1, 112 non_qos : 1, 113 power_mgmt : 1, 114 ast_index_timeout : 1, 115 ast_index_not_found : 1, 116 mcast_bcast : 1, 117 reserved_1a : 1, 118 first_mpdu : 1; 119 uint32_t msdu_done : 1, 120 reserved_2 : 17, 121 rx_bitmap_not_updated : 1, 122 decrypt_status_code : 3, 123 sa_is_valid : 1, 124 da_is_mcbc : 1, 125 da_is_valid : 1, 126 msdu_limit_error : 1, 127 da_idx_timeout : 1, 128 sa_idx_timeout : 1, 129 amsdu_parser_error : 1, 130 wifi_parser_error : 1, 131 flow_idx_invalid : 1, 132 flow_idx_timeout : 1; 133 uint32_t tlv64_padding : 32; 134 #endif 135 }; 136 137 138 139 140 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 141 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 142 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 143 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 144 145 146 147 148 #define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 149 #define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 150 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 151 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 152 153 154 155 156 #define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 157 #define RX_ATTENTION_RESERVED_0_LSB 9 158 #define RX_ATTENTION_RESERVED_0_MSB 15 159 #define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 160 161 162 163 164 #define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 165 #define RX_ATTENTION_PHY_PPDU_ID_LSB 16 166 #define RX_ATTENTION_PHY_PPDU_ID_MSB 31 167 #define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 168 169 170 171 172 #define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 173 #define RX_ATTENTION_FIRST_MPDU_LSB 32 174 #define RX_ATTENTION_FIRST_MPDU_MSB 32 175 #define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 176 177 178 179 180 #define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 181 #define RX_ATTENTION_RESERVED_1A_LSB 33 182 #define RX_ATTENTION_RESERVED_1A_MSB 33 183 #define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 184 185 186 187 188 #define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 189 #define RX_ATTENTION_MCAST_BCAST_LSB 34 190 #define RX_ATTENTION_MCAST_BCAST_MSB 34 191 #define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 192 193 194 195 196 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 197 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 198 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 199 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 200 201 202 203 204 #define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 205 #define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 206 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 207 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 208 209 210 211 212 #define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 213 #define RX_ATTENTION_POWER_MGMT_LSB 37 214 #define RX_ATTENTION_POWER_MGMT_MSB 37 215 #define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 216 217 218 219 220 #define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 221 #define RX_ATTENTION_NON_QOS_LSB 38 222 #define RX_ATTENTION_NON_QOS_MSB 38 223 #define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 224 225 226 227 228 #define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 229 #define RX_ATTENTION_NULL_DATA_LSB 39 230 #define RX_ATTENTION_NULL_DATA_MSB 39 231 #define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 232 233 234 235 236 #define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 237 #define RX_ATTENTION_MGMT_TYPE_LSB 40 238 #define RX_ATTENTION_MGMT_TYPE_MSB 40 239 #define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 240 241 242 243 244 #define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 245 #define RX_ATTENTION_CTRL_TYPE_LSB 41 246 #define RX_ATTENTION_CTRL_TYPE_MSB 41 247 #define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 248 249 250 251 252 #define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 253 #define RX_ATTENTION_MORE_DATA_LSB 42 254 #define RX_ATTENTION_MORE_DATA_MSB 42 255 #define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 256 257 258 259 260 #define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 261 #define RX_ATTENTION_EOSP_LSB 43 262 #define RX_ATTENTION_EOSP_MSB 43 263 #define RX_ATTENTION_EOSP_MASK 0x0000080000000000 264 265 266 267 268 #define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 269 #define RX_ATTENTION_A_MSDU_ERROR_LSB 44 270 #define RX_ATTENTION_A_MSDU_ERROR_MSB 44 271 #define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 272 273 274 275 276 #define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 277 #define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 278 #define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 279 #define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 280 281 282 283 284 #define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 285 #define RX_ATTENTION_ORDER_LSB 46 286 #define RX_ATTENTION_ORDER_MSB 46 287 #define RX_ATTENTION_ORDER_MASK 0x0000400000000000 288 289 290 291 292 #define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 293 #define RX_ATTENTION_CCE_MATCH_LSB 47 294 #define RX_ATTENTION_CCE_MATCH_MSB 47 295 #define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 296 297 298 299 300 #define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 301 #define RX_ATTENTION_OVERFLOW_ERR_LSB 48 302 #define RX_ATTENTION_OVERFLOW_ERR_MSB 48 303 #define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 304 305 306 307 308 #define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 309 #define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 310 #define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 311 #define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 312 313 314 315 316 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 317 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 318 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 319 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 320 321 322 323 324 #define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 325 #define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 326 #define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 327 #define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 328 329 330 331 332 #define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 333 #define RX_ATTENTION_SA_IDX_INVALID_LSB 52 334 #define RX_ATTENTION_SA_IDX_INVALID_MSB 52 335 #define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 336 337 338 339 340 #define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 341 #define RX_ATTENTION_DA_IDX_INVALID_LSB 53 342 #define RX_ATTENTION_DA_IDX_INVALID_MSB 53 343 #define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 344 345 346 347 348 #define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 349 #define RX_ATTENTION_RESERVED_1B_LSB 54 350 #define RX_ATTENTION_RESERVED_1B_MSB 54 351 #define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 352 353 354 355 356 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 357 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 358 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 359 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 360 361 362 363 364 #define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 365 #define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 366 #define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 367 #define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 368 369 370 371 372 #define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 373 #define RX_ATTENTION_DIRECTED_LSB 57 374 #define RX_ATTENTION_DIRECTED_MSB 57 375 #define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 376 377 378 379 380 #define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 381 #define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 382 #define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 383 #define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 384 385 386 387 388 #define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 389 #define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 390 #define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 391 #define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 392 393 394 395 396 #define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 397 #define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 398 #define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 399 #define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 400 401 402 403 404 #define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 405 #define RX_ATTENTION_DECRYPT_ERR_LSB 61 406 #define RX_ATTENTION_DECRYPT_ERR_MSB 61 407 #define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 408 409 410 411 412 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 413 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 414 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 415 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 416 417 418 419 420 #define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 421 #define RX_ATTENTION_FCS_ERR_LSB 63 422 #define RX_ATTENTION_FCS_ERR_MSB 63 423 #define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 424 425 426 427 428 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 429 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 430 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 431 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 432 433 434 435 436 #define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 437 #define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 438 #define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 439 #define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 440 441 442 443 444 #define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 445 #define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 446 #define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 447 #define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 448 449 450 451 452 #define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 453 #define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 454 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 455 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 456 457 458 459 460 #define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 461 #define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 462 #define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 463 #define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 464 465 466 467 468 #define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 469 #define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 470 #define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 471 #define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 472 473 474 475 476 #define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 477 #define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 478 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 479 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 480 481 482 483 484 #define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 485 #define RX_ATTENTION_DA_IS_VALID_LSB 7 486 #define RX_ATTENTION_DA_IS_VALID_MSB 7 487 #define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 488 489 490 491 492 #define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 493 #define RX_ATTENTION_DA_IS_MCBC_LSB 8 494 #define RX_ATTENTION_DA_IS_MCBC_MSB 8 495 #define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 496 497 498 499 500 #define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 501 #define RX_ATTENTION_SA_IS_VALID_LSB 9 502 #define RX_ATTENTION_SA_IS_VALID_MSB 9 503 #define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 504 505 506 507 508 #define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 509 #define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 510 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 511 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 512 513 514 515 516 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 517 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 518 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 519 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 520 521 522 523 524 #define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 525 #define RX_ATTENTION_RESERVED_2_LSB 14 526 #define RX_ATTENTION_RESERVED_2_MSB 30 527 #define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 528 529 530 531 532 #define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 533 #define RX_ATTENTION_MSDU_DONE_LSB 31 534 #define RX_ATTENTION_MSDU_DONE_MSB 31 535 #define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 536 537 538 539 540 #define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 541 #define RX_ATTENTION_TLV64_PADDING_LSB 32 542 #define RX_ATTENTION_TLV64_PADDING_MSB 63 543 #define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 544 545 546 547 #endif 548