1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_FRAME_1K_BITMAP_ACK_H_ 20 #define _RX_FRAME_1K_BITMAP_ACK_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 25 26 #define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 27 28 29 struct rx_frame_1k_bitmap_ack { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t reserved_0a : 5, 32 ba_bitmap_size : 2, 33 reserved_0b : 3, 34 ba_tid : 4, 35 sta_full_aid : 13, 36 reserved_0c : 5; 37 uint32_t addr1_31_0 : 32; 38 uint32_t addr1_47_32 : 16, 39 addr2_15_0 : 16; 40 uint32_t addr2_47_16 : 32; 41 uint32_t ba_ts_ctrl : 16, 42 ba_ts_seq : 16; 43 uint32_t ba_ts_bitmap_31_0 : 32; 44 uint32_t ba_ts_bitmap_63_32 : 32; 45 uint32_t ba_ts_bitmap_95_64 : 32; 46 uint32_t ba_ts_bitmap_127_96 : 32; 47 uint32_t ba_ts_bitmap_159_128 : 32; 48 uint32_t ba_ts_bitmap_191_160 : 32; 49 uint32_t ba_ts_bitmap_223_192 : 32; 50 uint32_t ba_ts_bitmap_255_224 : 32; 51 uint32_t ba_ts_bitmap_287_256 : 32; 52 uint32_t ba_ts_bitmap_319_288 : 32; 53 uint32_t ba_ts_bitmap_351_320 : 32; 54 uint32_t ba_ts_bitmap_383_352 : 32; 55 uint32_t ba_ts_bitmap_415_384 : 32; 56 uint32_t ba_ts_bitmap_447_416 : 32; 57 uint32_t ba_ts_bitmap_479_448 : 32; 58 uint32_t ba_ts_bitmap_511_480 : 32; 59 uint32_t ba_ts_bitmap_543_512 : 32; 60 uint32_t ba_ts_bitmap_575_544 : 32; 61 uint32_t ba_ts_bitmap_607_576 : 32; 62 uint32_t ba_ts_bitmap_639_608 : 32; 63 uint32_t ba_ts_bitmap_671_640 : 32; 64 uint32_t ba_ts_bitmap_703_672 : 32; 65 uint32_t ba_ts_bitmap_735_704 : 32; 66 uint32_t ba_ts_bitmap_767_736 : 32; 67 uint32_t ba_ts_bitmap_799_768 : 32; 68 uint32_t ba_ts_bitmap_831_800 : 32; 69 uint32_t ba_ts_bitmap_863_832 : 32; 70 uint32_t ba_ts_bitmap_895_864 : 32; 71 uint32_t ba_ts_bitmap_927_896 : 32; 72 uint32_t ba_ts_bitmap_959_928 : 32; 73 uint32_t ba_ts_bitmap_991_960 : 32; 74 uint32_t ba_ts_bitmap_1023_992 : 32; 75 uint32_t tlv64_padding : 32; 76 #else 77 uint32_t reserved_0c : 5, 78 sta_full_aid : 13, 79 ba_tid : 4, 80 reserved_0b : 3, 81 ba_bitmap_size : 2, 82 reserved_0a : 5; 83 uint32_t addr1_31_0 : 32; 84 uint32_t addr2_15_0 : 16, 85 addr1_47_32 : 16; 86 uint32_t addr2_47_16 : 32; 87 uint32_t ba_ts_seq : 16, 88 ba_ts_ctrl : 16; 89 uint32_t ba_ts_bitmap_31_0 : 32; 90 uint32_t ba_ts_bitmap_63_32 : 32; 91 uint32_t ba_ts_bitmap_95_64 : 32; 92 uint32_t ba_ts_bitmap_127_96 : 32; 93 uint32_t ba_ts_bitmap_159_128 : 32; 94 uint32_t ba_ts_bitmap_191_160 : 32; 95 uint32_t ba_ts_bitmap_223_192 : 32; 96 uint32_t ba_ts_bitmap_255_224 : 32; 97 uint32_t ba_ts_bitmap_287_256 : 32; 98 uint32_t ba_ts_bitmap_319_288 : 32; 99 uint32_t ba_ts_bitmap_351_320 : 32; 100 uint32_t ba_ts_bitmap_383_352 : 32; 101 uint32_t ba_ts_bitmap_415_384 : 32; 102 uint32_t ba_ts_bitmap_447_416 : 32; 103 uint32_t ba_ts_bitmap_479_448 : 32; 104 uint32_t ba_ts_bitmap_511_480 : 32; 105 uint32_t ba_ts_bitmap_543_512 : 32; 106 uint32_t ba_ts_bitmap_575_544 : 32; 107 uint32_t ba_ts_bitmap_607_576 : 32; 108 uint32_t ba_ts_bitmap_639_608 : 32; 109 uint32_t ba_ts_bitmap_671_640 : 32; 110 uint32_t ba_ts_bitmap_703_672 : 32; 111 uint32_t ba_ts_bitmap_735_704 : 32; 112 uint32_t ba_ts_bitmap_767_736 : 32; 113 uint32_t ba_ts_bitmap_799_768 : 32; 114 uint32_t ba_ts_bitmap_831_800 : 32; 115 uint32_t ba_ts_bitmap_863_832 : 32; 116 uint32_t ba_ts_bitmap_895_864 : 32; 117 uint32_t ba_ts_bitmap_927_896 : 32; 118 uint32_t ba_ts_bitmap_959_928 : 32; 119 uint32_t ba_ts_bitmap_991_960 : 32; 120 uint32_t ba_ts_bitmap_1023_992 : 32; 121 uint32_t tlv64_padding : 32; 122 #endif 123 }; 124 125 126 127 128 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 129 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 130 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 131 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f 132 133 134 135 136 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 137 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 138 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 139 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 140 141 142 143 144 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 145 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 146 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 147 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000380 148 149 150 151 152 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 153 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 154 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 155 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 156 157 158 159 160 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 161 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 162 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 163 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 164 165 166 167 168 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 169 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 170 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 171 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 172 173 174 175 176 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 177 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 32 178 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 63 179 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 180 181 182 183 184 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 185 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 186 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 187 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff 188 189 190 191 192 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 193 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 194 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 195 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 196 197 198 199 200 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 201 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 32 202 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 63 203 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 204 205 206 207 208 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 209 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 210 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 211 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff 212 213 214 215 216 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 217 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 218 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 219 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 220 221 222 223 224 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 225 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 226 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 227 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 228 229 230 231 232 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 233 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 234 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 235 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff 236 237 238 239 240 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 241 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 242 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 243 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 244 245 246 247 248 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 249 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 250 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 251 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff 252 253 254 255 256 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 257 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 258 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 259 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 260 261 262 263 264 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 265 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 266 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 267 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff 268 269 270 271 272 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 273 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 274 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 275 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 276 277 278 279 280 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 281 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 282 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 283 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff 284 285 286 287 288 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000030 289 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 32 290 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 63 291 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff00000000 292 293 294 295 296 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 297 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 298 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 299 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0x00000000ffffffff 300 301 302 303 304 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000038 305 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 32 306 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 63 307 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff00000000 308 309 310 311 312 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 313 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 314 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 315 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0x00000000ffffffff 316 317 318 319 320 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000040 321 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 32 322 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 63 323 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff00000000 324 325 326 327 328 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 329 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 330 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 331 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0x00000000ffffffff 332 333 334 335 336 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000048 337 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 32 338 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 63 339 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff00000000 340 341 342 343 344 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 345 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 346 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 347 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0x00000000ffffffff 348 349 350 351 352 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000050 353 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 32 354 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 63 355 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff00000000 356 357 358 359 360 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 361 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 362 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 363 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0x00000000ffffffff 364 365 366 367 368 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000058 369 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 32 370 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 63 371 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff00000000 372 373 374 375 376 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 377 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 378 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 379 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0x00000000ffffffff 380 381 382 383 384 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000060 385 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 32 386 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 63 387 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff00000000 388 389 390 391 392 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 393 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 394 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 395 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0x00000000ffffffff 396 397 398 399 400 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000068 401 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 32 402 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 63 403 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff00000000 404 405 406 407 408 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 409 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 410 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 411 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0x00000000ffffffff 412 413 414 415 416 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000070 417 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 32 418 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 63 419 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff00000000 420 421 422 423 424 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 425 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 426 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 427 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0x00000000ffffffff 428 429 430 431 432 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000078 433 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 32 434 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 63 435 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff00000000 436 437 438 439 440 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 441 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 442 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 443 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0x00000000ffffffff 444 445 446 447 448 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000080 449 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 32 450 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 63 451 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff00000000 452 453 454 455 456 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 457 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 458 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 459 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0x00000000ffffffff 460 461 462 463 464 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000088 465 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 32 466 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 63 467 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff00000000 468 469 470 471 472 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 473 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 474 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 475 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0x00000000ffffffff 476 477 478 479 480 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000090 481 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_LSB 32 482 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MSB 63 483 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 484 485 486 487 #endif 488