1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_FRAME_BITMAP_ACK_H_ 20 #define _RX_FRAME_BITMAP_ACK_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 25 26 #define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 27 28 29 struct rx_frame_bitmap_ack { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t no_bitmap_available : 1, 32 explicit_ack : 1, 33 explict_ack_type : 3, 34 ba_bitmap_size : 2, 35 reserved_0a : 3, 36 ba_tid : 4, 37 sta_full_aid : 13, 38 reserved_0b : 5; 39 uint32_t addr1_31_0 : 32; 40 uint32_t addr1_47_32 : 16, 41 addr2_15_0 : 16; 42 uint32_t addr2_47_16 : 32; 43 uint32_t ba_ts_ctrl : 16, 44 ba_ts_seq : 16; 45 uint32_t ba_ts_bitmap_31_0 : 32; 46 uint32_t ba_ts_bitmap_63_32 : 32; 47 uint32_t ba_ts_bitmap_95_64 : 32; 48 uint32_t ba_ts_bitmap_127_96 : 32; 49 uint32_t ba_ts_bitmap_159_128 : 32; 50 uint32_t ba_ts_bitmap_191_160 : 32; 51 uint32_t ba_ts_bitmap_223_192 : 32; 52 uint32_t ba_ts_bitmap_255_224 : 32; 53 uint32_t tlv64_padding : 32; 54 #else 55 uint32_t reserved_0b : 5, 56 sta_full_aid : 13, 57 ba_tid : 4, 58 reserved_0a : 3, 59 ba_bitmap_size : 2, 60 explict_ack_type : 3, 61 explicit_ack : 1, 62 no_bitmap_available : 1; 63 uint32_t addr1_31_0 : 32; 64 uint32_t addr2_15_0 : 16, 65 addr1_47_32 : 16; 66 uint32_t addr2_47_16 : 32; 67 uint32_t ba_ts_seq : 16, 68 ba_ts_ctrl : 16; 69 uint32_t ba_ts_bitmap_31_0 : 32; 70 uint32_t ba_ts_bitmap_63_32 : 32; 71 uint32_t ba_ts_bitmap_95_64 : 32; 72 uint32_t ba_ts_bitmap_127_96 : 32; 73 uint32_t ba_ts_bitmap_159_128 : 32; 74 uint32_t ba_ts_bitmap_191_160 : 32; 75 uint32_t ba_ts_bitmap_223_192 : 32; 76 uint32_t ba_ts_bitmap_255_224 : 32; 77 uint32_t tlv64_padding : 32; 78 #endif 79 }; 80 81 82 83 84 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 85 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 86 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 87 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 88 89 90 91 92 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 93 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 94 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 95 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 96 97 98 99 100 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 101 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 102 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 103 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c 104 105 106 107 108 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 109 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 110 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 111 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 112 113 114 115 116 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 117 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 118 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 119 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000380 120 121 122 123 124 #define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 125 #define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 126 #define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 127 #define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 128 129 130 131 132 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 133 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 134 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 135 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 136 137 138 139 140 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 141 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 142 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 143 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 144 145 146 147 148 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 149 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 32 150 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 63 151 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 152 153 154 155 156 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 157 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 158 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 159 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff 160 161 162 163 164 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 165 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 166 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 167 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 168 169 170 171 172 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 173 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 32 174 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 63 175 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 176 177 178 179 180 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 181 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 182 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 183 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff 184 185 186 187 188 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 189 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 190 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 191 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 192 193 194 195 196 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 197 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 198 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 199 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 200 201 202 203 204 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 205 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 206 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 207 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff 208 209 210 211 212 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 213 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 214 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 215 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 216 217 218 219 220 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 221 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 222 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 223 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff 224 225 226 227 228 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 229 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 230 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 231 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 232 233 234 235 236 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 237 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 238 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 239 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff 240 241 242 243 244 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 245 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 246 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 247 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 248 249 250 251 252 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 253 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 254 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 255 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff 256 257 258 259 260 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000030 261 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_LSB 32 262 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MSB 63 263 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 264 265 266 267 #endif 268