1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_MPDU_DESC_INFO_H_ 20 #define _RX_MPDU_DESC_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 25 26 27 struct rx_mpdu_desc_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t msdu_count : 8, 30 fragment_flag : 1, 31 mpdu_retry_bit : 1, 32 ampdu_flag : 1, 33 bar_frame : 1, 34 pn_fields_contain_valid_info : 1, 35 raw_mpdu : 1, 36 more_fragment_flag : 1, 37 src_info : 12, 38 mpdu_qos_control_valid : 1, 39 tid : 4; 40 uint32_t peer_meta_data : 32; 41 #else 42 uint32_t tid : 4, 43 mpdu_qos_control_valid : 1, 44 src_info : 12, 45 more_fragment_flag : 1, 46 raw_mpdu : 1, 47 pn_fields_contain_valid_info : 1, 48 bar_frame : 1, 49 ampdu_flag : 1, 50 mpdu_retry_bit : 1, 51 fragment_flag : 1, 52 msdu_count : 8; 53 uint32_t peer_meta_data : 32; 54 #endif 55 }; 56 57 58 59 60 #define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 61 #define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 62 #define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 63 #define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff 64 65 66 67 68 #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 69 #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 70 #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 71 #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 72 73 74 75 76 #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 77 #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 78 #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 79 #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 80 81 82 83 84 #define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 85 #define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 86 #define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 87 #define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 88 89 90 91 92 #define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 93 #define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 94 #define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 95 #define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 96 97 98 99 100 #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 101 #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 102 #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 103 #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 104 105 106 107 108 #define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 109 #define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 110 #define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 111 #define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 112 113 114 115 116 #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 117 #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 118 #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 119 #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 120 121 122 123 124 #define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 125 #define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 126 #define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 127 #define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 128 129 130 131 132 #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 133 #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 134 #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 135 #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 136 137 138 139 140 #define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 141 #define RX_MPDU_DESC_INFO_TID_LSB 28 142 #define RX_MPDU_DESC_INFO_TID_MSB 31 143 #define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 144 145 146 147 148 #define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 149 #define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 150 #define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 151 #define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff 152 153 154 155 #endif 156