1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_MPDU_END_H_ 20 #define _RX_MPDU_END_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RX_MPDU_END 4 25 26 #define NUM_OF_QWORDS_RX_MPDU_END 2 27 28 29 struct rx_mpdu_end { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t rxpcu_mpdu_filter_in_category : 2, 32 sw_frame_group_id : 7, 33 reserved_0 : 7, 34 phy_ppdu_id : 16; 35 uint32_t reserved_1a : 11, 36 unsup_ktype_short_frame : 1, 37 rx_in_tx_decrypt_byp : 1, 38 overflow_err : 1, 39 mpdu_length_err : 1, 40 tkip_mic_err : 1, 41 decrypt_err : 1, 42 unencrypted_frame_err : 1, 43 pn_fields_contain_valid_info : 1, 44 fcs_err : 1, 45 msdu_length_err : 1, 46 rxdma0_destination_ring : 3, 47 rxdma1_destination_ring : 3, 48 decrypt_status_code : 3, 49 rx_bitmap_not_updated : 1, 50 reserved_1b : 1; 51 uint32_t reserved_2a : 15, 52 rxpcu_mgmt_sequence_nr_valid : 1, 53 rxpcu_mgmt_sequence_nr : 16; 54 uint32_t rxframe_assert_mlo_timestamp : 32; 55 #else 56 uint32_t phy_ppdu_id : 16, 57 reserved_0 : 7, 58 sw_frame_group_id : 7, 59 rxpcu_mpdu_filter_in_category : 2; 60 uint32_t reserved_1b : 1, 61 rx_bitmap_not_updated : 1, 62 decrypt_status_code : 3, 63 rxdma1_destination_ring : 3, 64 rxdma0_destination_ring : 3, 65 msdu_length_err : 1, 66 fcs_err : 1, 67 pn_fields_contain_valid_info : 1, 68 unencrypted_frame_err : 1, 69 decrypt_err : 1, 70 tkip_mic_err : 1, 71 mpdu_length_err : 1, 72 overflow_err : 1, 73 rx_in_tx_decrypt_byp : 1, 74 unsup_ktype_short_frame : 1, 75 reserved_1a : 11; 76 uint32_t rxpcu_mgmt_sequence_nr : 16, 77 rxpcu_mgmt_sequence_nr_valid : 1, 78 reserved_2a : 15; 79 uint32_t rxframe_assert_mlo_timestamp : 32; 80 #endif 81 }; 82 83 84 85 86 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 87 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 88 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 89 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 90 91 92 93 94 #define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 95 #define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 96 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 97 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 98 99 100 101 102 #define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 103 #define RX_MPDU_END_RESERVED_0_LSB 9 104 #define RX_MPDU_END_RESERVED_0_MSB 15 105 #define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 106 107 108 109 110 #define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 111 #define RX_MPDU_END_PHY_PPDU_ID_LSB 16 112 #define RX_MPDU_END_PHY_PPDU_ID_MSB 31 113 #define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 114 115 116 117 118 #define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 119 #define RX_MPDU_END_RESERVED_1A_LSB 32 120 #define RX_MPDU_END_RESERVED_1A_MSB 42 121 #define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 122 123 124 125 126 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 127 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 128 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 129 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 130 131 132 133 134 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 135 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 136 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 137 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 138 139 140 141 142 #define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 143 #define RX_MPDU_END_OVERFLOW_ERR_LSB 45 144 #define RX_MPDU_END_OVERFLOW_ERR_MSB 45 145 #define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 146 147 148 149 150 #define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 151 #define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 152 #define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 153 #define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 154 155 156 157 158 #define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 159 #define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 160 #define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 161 #define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 162 163 164 165 166 #define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 167 #define RX_MPDU_END_DECRYPT_ERR_LSB 48 168 #define RX_MPDU_END_DECRYPT_ERR_MSB 48 169 #define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 170 171 172 173 174 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 175 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 176 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 177 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 178 179 180 181 182 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 183 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 184 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 185 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 186 187 188 189 190 #define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 191 #define RX_MPDU_END_FCS_ERR_LSB 51 192 #define RX_MPDU_END_FCS_ERR_MSB 51 193 #define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 194 195 196 197 198 #define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 199 #define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 200 #define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 201 #define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 202 203 204 205 206 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000 207 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53 208 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55 209 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000 210 211 212 213 214 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000 215 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56 216 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58 217 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000 218 219 220 221 222 #define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 223 #define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 224 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 225 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 226 227 228 229 230 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 231 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 232 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 233 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 234 235 236 237 238 #define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 239 #define RX_MPDU_END_RESERVED_1B_LSB 63 240 #define RX_MPDU_END_RESERVED_1B_MSB 63 241 #define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 242 243 244 245 246 #define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 247 #define RX_MPDU_END_RESERVED_2A_LSB 0 248 #define RX_MPDU_END_RESERVED_2A_MSB 14 249 #define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff 250 251 252 253 254 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 255 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 256 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 257 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 258 259 260 261 262 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 263 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 264 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 265 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 266 267 268 269 270 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008 271 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32 272 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63 273 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000 274 275 276 277 #endif 278