1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_MPDU_INFO_H_ 20 #define _RX_MPDU_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "rxpt_classify_info.h" 25 #define NUM_OF_DWORDS_RX_MPDU_INFO 30 26 27 28 struct rx_mpdu_info { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct rxpt_classify_info rxpt_classify_info_details; 31 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 32 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 33 receive_queue_number : 16, 34 pre_delim_err_warning : 1, 35 first_delim_err : 1, 36 reserved_2a : 6; 37 uint32_t pn_31_0 : 32; 38 uint32_t pn_63_32 : 32; 39 uint32_t pn_95_64 : 32; 40 uint32_t pn_127_96 : 32; 41 uint32_t epd_en : 1, 42 all_frames_shall_be_encrypted : 1, 43 encrypt_type : 4, 44 wep_key_width_for_variable_key : 2, 45 mesh_sta : 2, 46 bssid_hit : 1, 47 bssid_number : 4, 48 tid : 4, 49 reserved_7a : 13; 50 uint32_t peer_meta_data : 32; 51 uint32_t rxpcu_mpdu_filter_in_category : 2, 52 sw_frame_group_id : 7, 53 ndp_frame : 1, 54 phy_err : 1, 55 phy_err_during_mpdu_header : 1, 56 protocol_version_err : 1, 57 ast_based_lookup_valid : 1, 58 ranging : 1, 59 reserved_9a : 1, 60 phy_ppdu_id : 16; 61 uint32_t ast_index : 16, 62 sw_peer_id : 16; 63 uint32_t mpdu_frame_control_valid : 1, 64 mpdu_duration_valid : 1, 65 mac_addr_ad1_valid : 1, 66 mac_addr_ad2_valid : 1, 67 mac_addr_ad3_valid : 1, 68 mac_addr_ad4_valid : 1, 69 mpdu_sequence_control_valid : 1, 70 mpdu_qos_control_valid : 1, 71 mpdu_ht_control_valid : 1, 72 frame_encryption_info_valid : 1, 73 mpdu_fragment_number : 4, 74 more_fragment_flag : 1, 75 reserved_11a : 1, 76 fr_ds : 1, 77 to_ds : 1, 78 encrypted : 1, 79 mpdu_retry : 1, 80 mpdu_sequence_number : 12; 81 uint32_t key_id_octet : 8, 82 new_peer_entry : 1, 83 decrypt_needed : 1, 84 decap_type : 2, 85 rx_insert_vlan_c_tag_padding : 1, 86 rx_insert_vlan_s_tag_padding : 1, 87 strip_vlan_c_tag_decap : 1, 88 strip_vlan_s_tag_decap : 1, 89 pre_delim_count : 12, 90 ampdu_flag : 1, 91 bar_frame : 1, 92 raw_mpdu : 1, 93 reserved_12 : 1; 94 uint32_t mpdu_length : 14, 95 first_mpdu : 1, 96 mcast_bcast : 1, 97 ast_index_not_found : 1, 98 ast_index_timeout : 1, 99 power_mgmt : 1, 100 non_qos : 1, 101 null_data : 1, 102 mgmt_type : 1, 103 ctrl_type : 1, 104 more_data : 1, 105 eosp : 1, 106 fragment_flag : 1, 107 order : 1, 108 u_apsd_trigger : 1, 109 encrypt_required : 1, 110 directed : 1, 111 amsdu_present : 1, 112 reserved_13 : 1; 113 uint32_t mpdu_frame_control_field : 16, 114 mpdu_duration_field : 16; 115 uint32_t mac_addr_ad1_31_0 : 32; 116 uint32_t mac_addr_ad1_47_32 : 16, 117 mac_addr_ad2_15_0 : 16; 118 uint32_t mac_addr_ad2_47_16 : 32; 119 uint32_t mac_addr_ad3_31_0 : 32; 120 uint32_t mac_addr_ad3_47_32 : 16, 121 mpdu_sequence_control_field : 16; 122 uint32_t mac_addr_ad4_31_0 : 32; 123 uint32_t mac_addr_ad4_47_32 : 16, 124 mpdu_qos_control_field : 16; 125 uint32_t mpdu_ht_control_field : 32; 126 uint32_t vdev_id : 8, 127 service_code : 9, 128 priority_valid : 1, 129 src_info : 12, 130 reserved_23a : 1, 131 multi_link_addr_ad1_ad2_valid : 1; 132 uint32_t multi_link_addr_ad1_31_0 : 32; 133 uint32_t multi_link_addr_ad1_47_32 : 16, 134 multi_link_addr_ad2_15_0 : 16; 135 uint32_t multi_link_addr_ad2_47_16 : 32; 136 uint32_t authorized_to_send_wds : 1, 137 reserved_27a : 31; 138 uint32_t reserved_28a : 32; 139 uint32_t reserved_29a : 32; 140 #else 141 struct rxpt_classify_info rxpt_classify_info_details; 142 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 143 uint32_t reserved_2a : 6, 144 first_delim_err : 1, 145 pre_delim_err_warning : 1, 146 receive_queue_number : 16, 147 rx_reo_queue_desc_addr_39_32 : 8; 148 uint32_t pn_31_0 : 32; 149 uint32_t pn_63_32 : 32; 150 uint32_t pn_95_64 : 32; 151 uint32_t pn_127_96 : 32; 152 uint32_t reserved_7a : 13, 153 tid : 4, 154 bssid_number : 4, 155 bssid_hit : 1, 156 mesh_sta : 2, 157 wep_key_width_for_variable_key : 2, 158 encrypt_type : 4, 159 all_frames_shall_be_encrypted : 1, 160 epd_en : 1; 161 uint32_t peer_meta_data : 32; 162 uint32_t phy_ppdu_id : 16, 163 reserved_9a : 1, 164 ranging : 1, 165 ast_based_lookup_valid : 1, 166 protocol_version_err : 1, 167 phy_err_during_mpdu_header : 1, 168 phy_err : 1, 169 ndp_frame : 1, 170 sw_frame_group_id : 7, 171 rxpcu_mpdu_filter_in_category : 2; 172 uint32_t sw_peer_id : 16, 173 ast_index : 16; 174 uint32_t mpdu_sequence_number : 12, 175 mpdu_retry : 1, 176 encrypted : 1, 177 to_ds : 1, 178 fr_ds : 1, 179 reserved_11a : 1, 180 more_fragment_flag : 1, 181 mpdu_fragment_number : 4, 182 frame_encryption_info_valid : 1, 183 mpdu_ht_control_valid : 1, 184 mpdu_qos_control_valid : 1, 185 mpdu_sequence_control_valid : 1, 186 mac_addr_ad4_valid : 1, 187 mac_addr_ad3_valid : 1, 188 mac_addr_ad2_valid : 1, 189 mac_addr_ad1_valid : 1, 190 mpdu_duration_valid : 1, 191 mpdu_frame_control_valid : 1; 192 uint32_t reserved_12 : 1, 193 raw_mpdu : 1, 194 bar_frame : 1, 195 ampdu_flag : 1, 196 pre_delim_count : 12, 197 strip_vlan_s_tag_decap : 1, 198 strip_vlan_c_tag_decap : 1, 199 rx_insert_vlan_s_tag_padding : 1, 200 rx_insert_vlan_c_tag_padding : 1, 201 decap_type : 2, 202 decrypt_needed : 1, 203 new_peer_entry : 1, 204 key_id_octet : 8; 205 uint32_t reserved_13 : 1, 206 amsdu_present : 1, 207 directed : 1, 208 encrypt_required : 1, 209 u_apsd_trigger : 1, 210 order : 1, 211 fragment_flag : 1, 212 eosp : 1, 213 more_data : 1, 214 ctrl_type : 1, 215 mgmt_type : 1, 216 null_data : 1, 217 non_qos : 1, 218 power_mgmt : 1, 219 ast_index_timeout : 1, 220 ast_index_not_found : 1, 221 mcast_bcast : 1, 222 first_mpdu : 1, 223 mpdu_length : 14; 224 uint32_t mpdu_duration_field : 16, 225 mpdu_frame_control_field : 16; 226 uint32_t mac_addr_ad1_31_0 : 32; 227 uint32_t mac_addr_ad2_15_0 : 16, 228 mac_addr_ad1_47_32 : 16; 229 uint32_t mac_addr_ad2_47_16 : 32; 230 uint32_t mac_addr_ad3_31_0 : 32; 231 uint32_t mpdu_sequence_control_field : 16, 232 mac_addr_ad3_47_32 : 16; 233 uint32_t mac_addr_ad4_31_0 : 32; 234 uint32_t mpdu_qos_control_field : 16, 235 mac_addr_ad4_47_32 : 16; 236 uint32_t mpdu_ht_control_field : 32; 237 uint32_t multi_link_addr_ad1_ad2_valid : 1, 238 reserved_23a : 1, 239 src_info : 12, 240 priority_valid : 1, 241 service_code : 9, 242 vdev_id : 8; 243 uint32_t multi_link_addr_ad1_31_0 : 32; 244 uint32_t multi_link_addr_ad2_15_0 : 16, 245 multi_link_addr_ad1_47_32 : 16; 246 uint32_t multi_link_addr_ad2_47_16 : 32; 247 uint32_t reserved_27a : 31, 248 authorized_to_send_wds : 1; 249 uint32_t reserved_28a : 32; 250 uint32_t reserved_29a : 32; 251 #endif 252 }; 253 254 255 256 257 258 259 260 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 261 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 262 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 263 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 264 265 266 267 268 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 269 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 270 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 271 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 272 273 274 275 276 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 277 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 278 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 279 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 280 281 282 283 284 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 285 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 286 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 287 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 288 289 290 291 292 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 293 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 294 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 295 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 296 297 298 299 300 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 301 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 302 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 303 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 304 305 306 307 308 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 309 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 310 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 311 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 312 313 314 315 316 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 317 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 318 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 319 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 320 321 322 323 324 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 325 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 326 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 327 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 328 329 330 331 332 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 333 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 334 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 335 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 336 337 338 339 340 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 341 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 342 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 343 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 344 345 346 347 348 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 349 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 350 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 351 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 352 353 354 355 356 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 357 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 358 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 359 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 360 361 362 363 364 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 365 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 366 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 367 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffc00000 368 369 370 371 372 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 373 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 374 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 375 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 376 377 378 379 380 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 381 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 382 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 383 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 384 385 386 387 388 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 389 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 390 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 391 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 392 393 394 395 396 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 397 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 398 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 399 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 400 401 402 403 404 #define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x00000008 405 #define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 406 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 407 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 408 409 410 411 412 #define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x00000008 413 #define RX_MPDU_INFO_RESERVED_2A_LSB 26 414 #define RX_MPDU_INFO_RESERVED_2A_MSB 31 415 #define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 416 417 418 419 420 #define RX_MPDU_INFO_PN_31_0_OFFSET 0x0000000c 421 #define RX_MPDU_INFO_PN_31_0_LSB 0 422 #define RX_MPDU_INFO_PN_31_0_MSB 31 423 #define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff 424 425 426 427 428 #define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000010 429 #define RX_MPDU_INFO_PN_63_32_LSB 0 430 #define RX_MPDU_INFO_PN_63_32_MSB 31 431 #define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff 432 433 434 435 436 #define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000014 437 #define RX_MPDU_INFO_PN_95_64_LSB 0 438 #define RX_MPDU_INFO_PN_95_64_MSB 31 439 #define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff 440 441 442 443 444 #define RX_MPDU_INFO_PN_127_96_OFFSET 0x00000018 445 #define RX_MPDU_INFO_PN_127_96_LSB 0 446 #define RX_MPDU_INFO_PN_127_96_MSB 31 447 #define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff 448 449 450 451 452 #define RX_MPDU_INFO_EPD_EN_OFFSET 0x0000001c 453 #define RX_MPDU_INFO_EPD_EN_LSB 0 454 #define RX_MPDU_INFO_EPD_EN_MSB 0 455 #define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 456 457 458 459 460 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 461 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 462 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 463 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 464 465 466 467 468 #define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x0000001c 469 #define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 470 #define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 471 #define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c 472 473 474 475 476 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 477 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 478 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 479 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 480 481 482 483 484 #define RX_MPDU_INFO_MESH_STA_OFFSET 0x0000001c 485 #define RX_MPDU_INFO_MESH_STA_LSB 8 486 #define RX_MPDU_INFO_MESH_STA_MSB 9 487 #define RX_MPDU_INFO_MESH_STA_MASK 0x00000300 488 489 490 491 492 #define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x0000001c 493 #define RX_MPDU_INFO_BSSID_HIT_LSB 10 494 #define RX_MPDU_INFO_BSSID_HIT_MSB 10 495 #define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 496 497 498 499 500 #define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x0000001c 501 #define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 502 #define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 503 #define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 504 505 506 507 508 #define RX_MPDU_INFO_TID_OFFSET 0x0000001c 509 #define RX_MPDU_INFO_TID_LSB 15 510 #define RX_MPDU_INFO_TID_MSB 18 511 #define RX_MPDU_INFO_TID_MASK 0x00078000 512 513 514 515 516 #define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x0000001c 517 #define RX_MPDU_INFO_RESERVED_7A_LSB 19 518 #define RX_MPDU_INFO_RESERVED_7A_MSB 31 519 #define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 520 521 522 523 524 #define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000020 525 #define RX_MPDU_INFO_PEER_META_DATA_LSB 0 526 #define RX_MPDU_INFO_PEER_META_DATA_MSB 31 527 #define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff 528 529 530 531 532 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 533 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 534 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 535 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 536 537 538 539 540 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x00000024 541 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 542 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 543 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc 544 545 546 547 548 #define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x00000024 549 #define RX_MPDU_INFO_NDP_FRAME_LSB 9 550 #define RX_MPDU_INFO_NDP_FRAME_MSB 9 551 #define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 552 553 554 555 556 #define RX_MPDU_INFO_PHY_ERR_OFFSET 0x00000024 557 #define RX_MPDU_INFO_PHY_ERR_LSB 10 558 #define RX_MPDU_INFO_PHY_ERR_MSB 10 559 #define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 560 561 562 563 564 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 565 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 566 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 567 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 568 569 570 571 572 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 573 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 574 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 575 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 576 577 578 579 580 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 581 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 582 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 583 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 584 585 586 587 588 #define RX_MPDU_INFO_RANGING_OFFSET 0x00000024 589 #define RX_MPDU_INFO_RANGING_LSB 14 590 #define RX_MPDU_INFO_RANGING_MSB 14 591 #define RX_MPDU_INFO_RANGING_MASK 0x00004000 592 593 594 595 596 #define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x00000024 597 #define RX_MPDU_INFO_RESERVED_9A_LSB 15 598 #define RX_MPDU_INFO_RESERVED_9A_MSB 15 599 #define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 600 601 602 603 604 #define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x00000024 605 #define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 606 #define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 607 #define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 608 609 610 611 612 #define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 613 #define RX_MPDU_INFO_AST_INDEX_LSB 0 614 #define RX_MPDU_INFO_AST_INDEX_MSB 15 615 #define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff 616 617 618 619 620 #define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 621 #define RX_MPDU_INFO_SW_PEER_ID_LSB 16 622 #define RX_MPDU_INFO_SW_PEER_ID_MSB 31 623 #define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 624 625 626 627 628 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 629 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 630 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 631 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 632 633 634 635 636 #define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x0000002c 637 #define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 638 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 639 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 640 641 642 643 644 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 645 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 646 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 647 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 648 649 650 651 652 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 653 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 654 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 655 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 656 657 658 659 660 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 661 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 662 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 663 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 664 665 666 667 668 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 669 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 670 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 671 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 672 673 674 675 676 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 677 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 678 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 679 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 680 681 682 683 684 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 685 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 686 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 687 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 688 689 690 691 692 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 693 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 694 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 695 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 696 697 698 699 700 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 701 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 702 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 703 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 704 705 706 707 708 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 709 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 710 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 711 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 712 713 714 715 716 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 717 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 718 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 719 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 720 721 722 723 724 #define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x0000002c 725 #define RX_MPDU_INFO_RESERVED_11A_LSB 15 726 #define RX_MPDU_INFO_RESERVED_11A_MSB 15 727 #define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 728 729 730 731 732 #define RX_MPDU_INFO_FR_DS_OFFSET 0x0000002c 733 #define RX_MPDU_INFO_FR_DS_LSB 16 734 #define RX_MPDU_INFO_FR_DS_MSB 16 735 #define RX_MPDU_INFO_FR_DS_MASK 0x00010000 736 737 738 739 740 #define RX_MPDU_INFO_TO_DS_OFFSET 0x0000002c 741 #define RX_MPDU_INFO_TO_DS_LSB 17 742 #define RX_MPDU_INFO_TO_DS_MSB 17 743 #define RX_MPDU_INFO_TO_DS_MASK 0x00020000 744 745 746 747 748 #define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x0000002c 749 #define RX_MPDU_INFO_ENCRYPTED_LSB 18 750 #define RX_MPDU_INFO_ENCRYPTED_MSB 18 751 #define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 752 753 754 755 756 #define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x0000002c 757 #define RX_MPDU_INFO_MPDU_RETRY_LSB 19 758 #define RX_MPDU_INFO_MPDU_RETRY_MSB 19 759 #define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 760 761 762 763 764 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 765 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 766 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 767 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 768 769 770 771 772 #define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 773 #define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 774 #define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 775 #define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff 776 777 778 779 780 #define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 781 #define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 782 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 783 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 784 785 786 787 788 #define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 789 #define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 790 #define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 791 #define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 792 793 794 795 796 #define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 797 #define RX_MPDU_INFO_DECAP_TYPE_LSB 10 798 #define RX_MPDU_INFO_DECAP_TYPE_MSB 11 799 #define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 800 801 802 803 804 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 805 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 806 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 807 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 808 809 810 811 812 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 813 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 814 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 815 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 816 817 818 819 820 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 821 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 822 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 823 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 824 825 826 827 828 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 829 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 830 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 831 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 832 833 834 835 836 #define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 837 #define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 838 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 839 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 840 841 842 843 844 #define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 845 #define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 846 #define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 847 #define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 848 849 850 851 852 #define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 853 #define RX_MPDU_INFO_BAR_FRAME_LSB 29 854 #define RX_MPDU_INFO_BAR_FRAME_MSB 29 855 #define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 856 857 858 859 860 #define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 861 #define RX_MPDU_INFO_RAW_MPDU_LSB 30 862 #define RX_MPDU_INFO_RAW_MPDU_MSB 30 863 #define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 864 865 866 867 868 #define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 869 #define RX_MPDU_INFO_RESERVED_12_LSB 31 870 #define RX_MPDU_INFO_RESERVED_12_MSB 31 871 #define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 872 873 874 875 876 #define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 877 #define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 878 #define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 879 #define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff 880 881 882 883 884 #define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 885 #define RX_MPDU_INFO_FIRST_MPDU_LSB 14 886 #define RX_MPDU_INFO_FIRST_MPDU_MSB 14 887 #define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 888 889 890 891 892 #define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 893 #define RX_MPDU_INFO_MCAST_BCAST_LSB 15 894 #define RX_MPDU_INFO_MCAST_BCAST_MSB 15 895 #define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 896 897 898 899 900 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 901 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 902 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 903 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 904 905 906 907 908 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 909 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 910 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 911 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 912 913 914 915 916 #define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 917 #define RX_MPDU_INFO_POWER_MGMT_LSB 18 918 #define RX_MPDU_INFO_POWER_MGMT_MSB 18 919 #define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 920 921 922 923 924 #define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 925 #define RX_MPDU_INFO_NON_QOS_LSB 19 926 #define RX_MPDU_INFO_NON_QOS_MSB 19 927 #define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 928 929 930 931 932 #define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 933 #define RX_MPDU_INFO_NULL_DATA_LSB 20 934 #define RX_MPDU_INFO_NULL_DATA_MSB 20 935 #define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 936 937 938 939 940 #define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 941 #define RX_MPDU_INFO_MGMT_TYPE_LSB 21 942 #define RX_MPDU_INFO_MGMT_TYPE_MSB 21 943 #define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 944 945 946 947 948 #define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 949 #define RX_MPDU_INFO_CTRL_TYPE_LSB 22 950 #define RX_MPDU_INFO_CTRL_TYPE_MSB 22 951 #define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 952 953 954 955 956 #define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 957 #define RX_MPDU_INFO_MORE_DATA_LSB 23 958 #define RX_MPDU_INFO_MORE_DATA_MSB 23 959 #define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 960 961 962 963 964 #define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 965 #define RX_MPDU_INFO_EOSP_LSB 24 966 #define RX_MPDU_INFO_EOSP_MSB 24 967 #define RX_MPDU_INFO_EOSP_MASK 0x01000000 968 969 970 971 972 #define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 973 #define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 974 #define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 975 #define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 976 977 978 979 980 #define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 981 #define RX_MPDU_INFO_ORDER_LSB 26 982 #define RX_MPDU_INFO_ORDER_MSB 26 983 #define RX_MPDU_INFO_ORDER_MASK 0x04000000 984 985 986 987 988 #define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 989 #define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 990 #define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 991 #define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 992 993 994 995 996 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 997 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 998 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 999 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 1000 1001 1002 1003 1004 #define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 1005 #define RX_MPDU_INFO_DIRECTED_LSB 29 1006 #define RX_MPDU_INFO_DIRECTED_MSB 29 1007 #define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 1008 1009 1010 1011 1012 #define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 1013 #define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 1014 #define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 1015 #define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 1016 1017 1018 1019 1020 #define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 1021 #define RX_MPDU_INFO_RESERVED_13_LSB 31 1022 #define RX_MPDU_INFO_RESERVED_13_MSB 31 1023 #define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 1024 1025 1026 1027 1028 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 1029 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 1030 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 1031 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 1032 1033 1034 1035 1036 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 1037 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 1038 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 1039 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 1040 1041 1042 1043 1044 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 1045 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 1046 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 1047 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff 1048 1049 1050 1051 1052 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 1053 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 1054 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 1055 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 1056 1057 1058 1059 1060 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 1061 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 1062 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 1063 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 1064 1065 1066 1067 1068 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 1069 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 1070 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 1071 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff 1072 1073 1074 1075 1076 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 1077 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 1078 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 1079 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff 1080 1081 1082 1083 1084 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 1085 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 1086 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 1087 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 1088 1089 1090 1091 1092 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 1093 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 1094 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 1095 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 1096 1097 1098 1099 1100 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 1101 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 1102 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 1103 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff 1104 1105 1106 1107 1108 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 1109 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 1110 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 1111 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 1112 1113 1114 1115 1116 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 1117 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 1118 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 1119 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 1120 1121 1122 1123 1124 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 1125 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 1126 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 1127 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 1128 1129 1130 1131 1132 #define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c 1133 #define RX_MPDU_INFO_VDEV_ID_LSB 0 1134 #define RX_MPDU_INFO_VDEV_ID_MSB 7 1135 #define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff 1136 1137 1138 1139 1140 #define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c 1141 #define RX_MPDU_INFO_SERVICE_CODE_LSB 8 1142 #define RX_MPDU_INFO_SERVICE_CODE_MSB 16 1143 #define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 1144 1145 1146 1147 1148 #define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c 1149 #define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 1150 #define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 1151 #define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 1152 1153 1154 1155 1156 #define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c 1157 #define RX_MPDU_INFO_SRC_INFO_LSB 18 1158 #define RX_MPDU_INFO_SRC_INFO_MSB 29 1159 #define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 1160 1161 1162 1163 1164 #define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c 1165 #define RX_MPDU_INFO_RESERVED_23A_LSB 30 1166 #define RX_MPDU_INFO_RESERVED_23A_MSB 30 1167 #define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 1168 1169 1170 1171 1172 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000005c 1173 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 31 1174 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 31 1175 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x80000000 1176 1177 1178 1179 1180 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x00000060 1181 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_LSB 0 1182 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MSB 31 1183 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MASK 0xffffffff 1184 1185 1186 1187 1188 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x00000064 1189 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_LSB 0 1190 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MSB 15 1191 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff 1192 1193 1194 1195 1196 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x00000064 1197 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_LSB 16 1198 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MSB 31 1199 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff0000 1200 1201 1202 1203 1204 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x00000068 1205 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_LSB 0 1206 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MSB 31 1207 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MASK 0xffffffff 1208 1209 1210 1211 1212 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c 1213 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 1214 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 1215 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 1216 1217 1218 1219 1220 #define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c 1221 #define RX_MPDU_INFO_RESERVED_27A_LSB 1 1222 #define RX_MPDU_INFO_RESERVED_27A_MSB 31 1223 #define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe 1224 1225 1226 1227 1228 #define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 1229 #define RX_MPDU_INFO_RESERVED_28A_LSB 0 1230 #define RX_MPDU_INFO_RESERVED_28A_MSB 31 1231 #define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff 1232 1233 1234 1235 1236 #define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 1237 #define RX_MPDU_INFO_RESERVED_29A_LSB 0 1238 #define RX_MPDU_INFO_RESERVED_29A_MSB 31 1239 #define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff 1240 1241 1242 1243 #endif 1244