1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_MSDU_DESC_INFO_H_ 20 #define _RX_MSDU_DESC_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 25 26 27 struct rx_msdu_desc_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t first_msdu_in_mpdu_flag : 1, 30 last_msdu_in_mpdu_flag : 1, 31 msdu_continuation : 1, 32 msdu_length : 14, 33 msdu_drop : 1, 34 sa_is_valid : 1, 35 da_is_valid : 1, 36 da_is_mcbc : 1, 37 l3_header_padding_msb : 1, 38 tcp_udp_chksum_fail : 1, 39 ip_chksum_fail : 1, 40 fr_ds : 1, 41 to_ds : 1, 42 intra_bss : 1, 43 dest_chip_id : 2, 44 decap_format : 2, 45 dest_chip_pmac_id : 1; 46 #else 47 uint32_t dest_chip_pmac_id : 1, 48 decap_format : 2, 49 dest_chip_id : 2, 50 intra_bss : 1, 51 to_ds : 1, 52 fr_ds : 1, 53 ip_chksum_fail : 1, 54 tcp_udp_chksum_fail : 1, 55 l3_header_padding_msb : 1, 56 da_is_mcbc : 1, 57 da_is_valid : 1, 58 sa_is_valid : 1, 59 msdu_drop : 1, 60 msdu_length : 14, 61 msdu_continuation : 1, 62 last_msdu_in_mpdu_flag : 1, 63 first_msdu_in_mpdu_flag : 1; 64 #endif 65 }; 66 67 68 69 70 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 71 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 72 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 73 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 74 75 76 77 78 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 79 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 80 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 81 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 82 83 84 85 86 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 87 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 88 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 89 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 90 91 92 93 94 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 95 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 96 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 97 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 98 99 100 101 102 #define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 103 #define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 104 #define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 105 #define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 106 107 108 109 110 #define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 111 #define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 112 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 113 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 114 115 116 117 118 #define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 119 #define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 120 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 121 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 122 123 124 125 126 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 127 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 128 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 129 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 130 131 132 133 134 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 135 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 136 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 137 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 138 139 140 141 142 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 143 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 144 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 145 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 146 147 148 149 150 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 151 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 152 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 153 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 154 155 156 157 158 #define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 159 #define RX_MSDU_DESC_INFO_FR_DS_LSB 24 160 #define RX_MSDU_DESC_INFO_FR_DS_MSB 24 161 #define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 162 163 164 165 166 #define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 167 #define RX_MSDU_DESC_INFO_TO_DS_LSB 25 168 #define RX_MSDU_DESC_INFO_TO_DS_MSB 25 169 #define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 170 171 172 173 174 #define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 175 #define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 176 #define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 177 #define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 178 179 180 181 182 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 183 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 184 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 185 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 186 187 188 189 190 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 191 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 192 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 193 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 194 195 196 197 198 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_OFFSET 0x00000000 199 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_LSB 31 200 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_MSB 31 201 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_MASK 0x80000000 202 203 204 205 #endif 206