1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_MSDU_END_H_ 20 #define _RX_MSDU_END_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RX_MSDU_END 32 25 26 #define NUM_OF_QWORDS_RX_MSDU_END 16 27 28 29 struct rx_msdu_end { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t rxpcu_mpdu_filter_in_category : 2, 32 sw_frame_group_id : 7, 33 reserved_0 : 7, 34 phy_ppdu_id : 16; 35 uint32_t ip_hdr_chksum : 16, 36 reported_mpdu_length : 14, 37 reserved_1a : 2; 38 uint32_t reserved_2a : 8, 39 cce_super_rule : 6, 40 cce_classify_not_done_truncate : 1, 41 cce_classify_not_done_cce_dis : 1, 42 cumulative_l3_checksum : 16; 43 uint32_t rule_indication_31_0 : 32; 44 uint32_t ipv6_options_crc : 32; 45 uint32_t da_offset : 6, 46 sa_offset : 6, 47 da_offset_valid : 1, 48 sa_offset_valid : 1, 49 reserved_5a : 2, 50 l3_type : 16; 51 uint32_t rule_indication_63_32 : 32; 52 uint32_t tcp_seq_number : 32; 53 uint32_t tcp_ack_number : 32; 54 uint32_t tcp_flag : 9, 55 lro_eligible : 1, 56 reserved_9a : 6, 57 window_size : 16; 58 uint32_t sa_sw_peer_id : 16, 59 sa_idx_timeout : 1, 60 da_idx_timeout : 1, 61 to_ds : 1, 62 tid : 4, 63 sa_is_valid : 1, 64 da_is_valid : 1, 65 da_is_mcbc : 1, 66 l3_header_padding : 2, 67 first_msdu : 1, 68 last_msdu : 1, 69 fr_ds : 1, 70 ip_chksum_fail_copy : 1; 71 uint32_t sa_idx : 16, 72 da_idx_or_sw_peer_id : 16; 73 uint32_t msdu_drop : 1, 74 reo_destination_indication : 5, 75 flow_idx : 20, 76 use_ppe : 1, 77 mesh_sta : 2, 78 vlan_ctag_stripped : 1, 79 vlan_stag_stripped : 1, 80 fragment_flag : 1; 81 uint32_t fse_metadata : 32; 82 uint32_t cce_metadata : 16, 83 tcp_udp_chksum : 16; 84 uint32_t aggregation_count : 8, 85 flow_aggregation_continuation : 1, 86 fisa_timeout : 1, 87 tcp_udp_chksum_fail_copy : 1, 88 msdu_limit_error : 1, 89 flow_idx_timeout : 1, 90 flow_idx_invalid : 1, 91 cce_match : 1, 92 amsdu_parser_error : 1, 93 cumulative_ip_length : 16; 94 uint32_t key_id_octet : 8, 95 reserved_16a : 24; 96 uint32_t reserved_17a : 6, 97 service_code : 9, 98 priority_valid : 1, 99 intra_bss : 1, 100 dest_chip_id : 2, 101 multicast_echo : 1, 102 wds_learning_event : 1, 103 wds_roaming_event : 1, 104 wds_keep_alive_event : 1, 105 dest_chip_pmac_id : 1, 106 reserved_17b : 8; 107 uint32_t msdu_length : 14, 108 stbc : 1, 109 ipsec_esp : 1, 110 l3_offset : 7, 111 ipsec_ah : 1, 112 l4_offset : 8; 113 uint32_t msdu_number : 8, 114 decap_format : 2, 115 ipv4_proto : 1, 116 ipv6_proto : 1, 117 tcp_proto : 1, 118 udp_proto : 1, 119 ip_frag : 1, 120 tcp_only_ack : 1, 121 da_is_bcast_mcast : 1, 122 toeplitz_hash_sel : 2, 123 ip_fixed_header_valid : 1, 124 ip_extn_header_valid : 1, 125 tcp_udp_header_valid : 1, 126 mesh_control_present : 1, 127 ldpc : 1, 128 ip4_protocol_ip6_next_header : 8; 129 uint32_t vlan_ctag_ci : 16, 130 vlan_stag_ci : 16; 131 uint32_t peer_meta_data : 32; 132 uint32_t user_rssi : 8, 133 pkt_type : 4, 134 sgi : 2, 135 rate_mcs : 4, 136 receive_bandwidth : 3, 137 reception_type : 3, 138 mimo_ss_bitmap : 7, 139 msdu_done_copy : 1; 140 uint32_t flow_id_toeplitz : 32; 141 uint32_t ppdu_start_timestamp_63_32 : 32; 142 uint32_t sw_phy_meta_data : 32; 143 uint32_t ppdu_start_timestamp_31_0 : 32; 144 uint32_t toeplitz_hash_2_or_4 : 32; 145 uint32_t reserved_28a : 16, 146 sa_15_0 : 16; 147 uint32_t sa_47_16 : 32; 148 uint32_t first_mpdu : 1, 149 reserved_30a : 1, 150 mcast_bcast : 1, 151 ast_index_not_found : 1, 152 ast_index_timeout : 1, 153 power_mgmt : 1, 154 non_qos : 1, 155 null_data : 1, 156 mgmt_type : 1, 157 ctrl_type : 1, 158 more_data : 1, 159 eosp : 1, 160 a_msdu_error : 1, 161 reserved_30b : 1, 162 order : 1, 163 wifi_parser_error : 1, 164 overflow_err : 1, 165 msdu_length_err : 1, 166 tcp_udp_chksum_fail : 1, 167 ip_chksum_fail : 1, 168 sa_idx_invalid : 1, 169 da_idx_invalid : 1, 170 amsdu_addr_mismatch : 1, 171 rx_in_tx_decrypt_byp : 1, 172 encrypt_required : 1, 173 directed : 1, 174 buffer_fragment : 1, 175 mpdu_length_err : 1, 176 tkip_mic_err : 1, 177 decrypt_err : 1, 178 unencrypted_frame_err : 1, 179 fcs_err : 1; 180 uint32_t reserved_31a : 10, 181 decrypt_status_code : 3, 182 rx_bitmap_not_updated : 1, 183 reserved_31b : 17, 184 msdu_done : 1; 185 #else 186 uint32_t phy_ppdu_id : 16, 187 reserved_0 : 7, 188 sw_frame_group_id : 7, 189 rxpcu_mpdu_filter_in_category : 2; 190 uint32_t reserved_1a : 2, 191 reported_mpdu_length : 14, 192 ip_hdr_chksum : 16; 193 uint32_t cumulative_l3_checksum : 16, 194 cce_classify_not_done_cce_dis : 1, 195 cce_classify_not_done_truncate : 1, 196 cce_super_rule : 6, 197 reserved_2a : 8; 198 uint32_t rule_indication_31_0 : 32; 199 uint32_t ipv6_options_crc : 32; 200 uint32_t l3_type : 16, 201 reserved_5a : 2, 202 sa_offset_valid : 1, 203 da_offset_valid : 1, 204 sa_offset : 6, 205 da_offset : 6; 206 uint32_t rule_indication_63_32 : 32; 207 uint32_t tcp_seq_number : 32; 208 uint32_t tcp_ack_number : 32; 209 uint32_t window_size : 16, 210 reserved_9a : 6, 211 lro_eligible : 1, 212 tcp_flag : 9; 213 uint32_t ip_chksum_fail_copy : 1, 214 fr_ds : 1, 215 last_msdu : 1, 216 first_msdu : 1, 217 l3_header_padding : 2, 218 da_is_mcbc : 1, 219 da_is_valid : 1, 220 sa_is_valid : 1, 221 tid : 4, 222 to_ds : 1, 223 da_idx_timeout : 1, 224 sa_idx_timeout : 1, 225 sa_sw_peer_id : 16; 226 uint32_t da_idx_or_sw_peer_id : 16, 227 sa_idx : 16; 228 uint32_t fragment_flag : 1, 229 vlan_stag_stripped : 1, 230 vlan_ctag_stripped : 1, 231 mesh_sta : 2, 232 use_ppe : 1, 233 flow_idx : 20, 234 reo_destination_indication : 5, 235 msdu_drop : 1; 236 uint32_t fse_metadata : 32; 237 uint32_t tcp_udp_chksum : 16, 238 cce_metadata : 16; 239 uint32_t cumulative_ip_length : 16, 240 amsdu_parser_error : 1, 241 cce_match : 1, 242 flow_idx_invalid : 1, 243 flow_idx_timeout : 1, 244 msdu_limit_error : 1, 245 tcp_udp_chksum_fail_copy : 1, 246 fisa_timeout : 1, 247 flow_aggregation_continuation : 1, 248 aggregation_count : 8; 249 uint32_t reserved_16a : 24, 250 key_id_octet : 8; 251 uint32_t reserved_17b : 8, 252 dest_chip_pmac_id : 1, 253 wds_keep_alive_event : 1, 254 wds_roaming_event : 1, 255 wds_learning_event : 1, 256 multicast_echo : 1, 257 dest_chip_id : 2, 258 intra_bss : 1, 259 priority_valid : 1, 260 service_code : 9, 261 reserved_17a : 6; 262 uint32_t l4_offset : 8, 263 ipsec_ah : 1, 264 l3_offset : 7, 265 ipsec_esp : 1, 266 stbc : 1, 267 msdu_length : 14; 268 uint32_t ip4_protocol_ip6_next_header : 8, 269 ldpc : 1, 270 mesh_control_present : 1, 271 tcp_udp_header_valid : 1, 272 ip_extn_header_valid : 1, 273 ip_fixed_header_valid : 1, 274 toeplitz_hash_sel : 2, 275 da_is_bcast_mcast : 1, 276 tcp_only_ack : 1, 277 ip_frag : 1, 278 udp_proto : 1, 279 tcp_proto : 1, 280 ipv6_proto : 1, 281 ipv4_proto : 1, 282 decap_format : 2, 283 msdu_number : 8; 284 uint32_t vlan_stag_ci : 16, 285 vlan_ctag_ci : 16; 286 uint32_t peer_meta_data : 32; 287 uint32_t msdu_done_copy : 1, 288 mimo_ss_bitmap : 7, 289 reception_type : 3, 290 receive_bandwidth : 3, 291 rate_mcs : 4, 292 sgi : 2, 293 pkt_type : 4, 294 user_rssi : 8; 295 uint32_t flow_id_toeplitz : 32; 296 uint32_t ppdu_start_timestamp_63_32 : 32; 297 uint32_t sw_phy_meta_data : 32; 298 uint32_t ppdu_start_timestamp_31_0 : 32; 299 uint32_t toeplitz_hash_2_or_4 : 32; 300 uint32_t sa_15_0 : 16, 301 reserved_28a : 16; 302 uint32_t sa_47_16 : 32; 303 uint32_t fcs_err : 1, 304 unencrypted_frame_err : 1, 305 decrypt_err : 1, 306 tkip_mic_err : 1, 307 mpdu_length_err : 1, 308 buffer_fragment : 1, 309 directed : 1, 310 encrypt_required : 1, 311 rx_in_tx_decrypt_byp : 1, 312 amsdu_addr_mismatch : 1, 313 da_idx_invalid : 1, 314 sa_idx_invalid : 1, 315 ip_chksum_fail : 1, 316 tcp_udp_chksum_fail : 1, 317 msdu_length_err : 1, 318 overflow_err : 1, 319 wifi_parser_error : 1, 320 order : 1, 321 reserved_30b : 1, 322 a_msdu_error : 1, 323 eosp : 1, 324 more_data : 1, 325 ctrl_type : 1, 326 mgmt_type : 1, 327 null_data : 1, 328 non_qos : 1, 329 power_mgmt : 1, 330 ast_index_timeout : 1, 331 ast_index_not_found : 1, 332 mcast_bcast : 1, 333 reserved_30a : 1, 334 first_mpdu : 1; 335 uint32_t msdu_done : 1, 336 reserved_31b : 17, 337 rx_bitmap_not_updated : 1, 338 decrypt_status_code : 3, 339 reserved_31a : 10; 340 #endif 341 }; 342 343 344 345 346 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 347 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 348 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 349 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 350 351 352 353 354 #define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 355 #define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 356 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 357 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 358 359 360 361 362 #define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 363 #define RX_MSDU_END_RESERVED_0_LSB 9 364 #define RX_MSDU_END_RESERVED_0_MSB 15 365 #define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 366 367 368 369 370 #define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 371 #define RX_MSDU_END_PHY_PPDU_ID_LSB 16 372 #define RX_MSDU_END_PHY_PPDU_ID_MSB 31 373 #define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 374 375 376 377 378 #define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 379 #define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 380 #define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 381 #define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 382 383 384 385 386 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 387 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 388 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 389 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 390 391 392 393 394 #define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 395 #define RX_MSDU_END_RESERVED_1A_LSB 62 396 #define RX_MSDU_END_RESERVED_1A_MSB 63 397 #define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 398 399 400 401 402 #define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 403 #define RX_MSDU_END_RESERVED_2A_LSB 0 404 #define RX_MSDU_END_RESERVED_2A_MSB 7 405 #define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff 406 407 408 409 410 #define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 411 #define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 412 #define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 413 #define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 414 415 416 417 418 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 419 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 420 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 421 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 422 423 424 425 426 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 427 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 428 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 429 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 430 431 432 433 434 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 435 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 436 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 437 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 438 439 440 441 442 #define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 443 #define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 444 #define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 445 #define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 446 447 448 449 450 #define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 451 #define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 452 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 453 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff 454 455 456 457 458 #define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 459 #define RX_MSDU_END_DA_OFFSET_LSB 32 460 #define RX_MSDU_END_DA_OFFSET_MSB 37 461 #define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 462 463 464 465 466 #define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 467 #define RX_MSDU_END_SA_OFFSET_LSB 38 468 #define RX_MSDU_END_SA_OFFSET_MSB 43 469 #define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 470 471 472 473 474 #define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 475 #define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 476 #define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 477 #define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 478 479 480 481 482 #define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 483 #define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 484 #define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 485 #define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 486 487 488 489 490 #define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 491 #define RX_MSDU_END_RESERVED_5A_LSB 46 492 #define RX_MSDU_END_RESERVED_5A_MSB 47 493 #define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 494 495 496 497 498 #define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 499 #define RX_MSDU_END_L3_TYPE_LSB 48 500 #define RX_MSDU_END_L3_TYPE_MSB 63 501 #define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 502 503 504 505 506 #define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 507 #define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 508 #define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 509 #define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff 510 511 512 513 514 #define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 515 #define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 516 #define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 517 #define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 518 519 520 521 522 #define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 523 #define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 524 #define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 525 #define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff 526 527 528 529 530 #define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 531 #define RX_MSDU_END_TCP_FLAG_LSB 32 532 #define RX_MSDU_END_TCP_FLAG_MSB 40 533 #define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 534 535 536 537 538 #define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 539 #define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 540 #define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 541 #define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 542 543 544 545 546 #define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 547 #define RX_MSDU_END_RESERVED_9A_LSB 42 548 #define RX_MSDU_END_RESERVED_9A_MSB 47 549 #define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 550 551 552 553 554 #define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 555 #define RX_MSDU_END_WINDOW_SIZE_LSB 48 556 #define RX_MSDU_END_WINDOW_SIZE_MSB 63 557 #define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 558 559 560 561 562 #define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 563 #define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 564 #define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 565 #define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff 566 567 568 569 570 #define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 571 #define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 572 #define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 573 #define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 574 575 576 577 578 #define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 579 #define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 580 #define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 581 #define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 582 583 584 585 586 #define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 587 #define RX_MSDU_END_TO_DS_LSB 18 588 #define RX_MSDU_END_TO_DS_MSB 18 589 #define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 590 591 592 593 594 #define RX_MSDU_END_TID_OFFSET 0x0000000000000028 595 #define RX_MSDU_END_TID_LSB 19 596 #define RX_MSDU_END_TID_MSB 22 597 #define RX_MSDU_END_TID_MASK 0x0000000000780000 598 599 600 601 602 #define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 603 #define RX_MSDU_END_SA_IS_VALID_LSB 23 604 #define RX_MSDU_END_SA_IS_VALID_MSB 23 605 #define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 606 607 608 609 610 #define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 611 #define RX_MSDU_END_DA_IS_VALID_LSB 24 612 #define RX_MSDU_END_DA_IS_VALID_MSB 24 613 #define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 614 615 616 617 618 #define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 619 #define RX_MSDU_END_DA_IS_MCBC_LSB 25 620 #define RX_MSDU_END_DA_IS_MCBC_MSB 25 621 #define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 622 623 624 625 626 #define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 627 #define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 628 #define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 629 #define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 630 631 632 633 634 #define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 635 #define RX_MSDU_END_FIRST_MSDU_LSB 28 636 #define RX_MSDU_END_FIRST_MSDU_MSB 28 637 #define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 638 639 640 641 642 #define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 643 #define RX_MSDU_END_LAST_MSDU_LSB 29 644 #define RX_MSDU_END_LAST_MSDU_MSB 29 645 #define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 646 647 648 649 650 #define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 651 #define RX_MSDU_END_FR_DS_LSB 30 652 #define RX_MSDU_END_FR_DS_MSB 30 653 #define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 654 655 656 657 658 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 659 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 660 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 661 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 662 663 664 665 666 #define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 667 #define RX_MSDU_END_SA_IDX_LSB 32 668 #define RX_MSDU_END_SA_IDX_MSB 47 669 #define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 670 671 672 673 674 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 675 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 676 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 677 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 678 679 680 681 682 #define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 683 #define RX_MSDU_END_MSDU_DROP_LSB 0 684 #define RX_MSDU_END_MSDU_DROP_MSB 0 685 #define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 686 687 688 689 690 #define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 691 #define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 692 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 693 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e 694 695 696 697 698 #define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 699 #define RX_MSDU_END_FLOW_IDX_LSB 6 700 #define RX_MSDU_END_FLOW_IDX_MSB 25 701 #define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 702 703 704 705 706 #define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 707 #define RX_MSDU_END_USE_PPE_LSB 26 708 #define RX_MSDU_END_USE_PPE_MSB 26 709 #define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 710 711 712 713 714 #define RX_MSDU_END_MESH_STA_OFFSET 0x0000000000000030 715 #define RX_MSDU_END_MESH_STA_LSB 27 716 #define RX_MSDU_END_MESH_STA_MSB 28 717 #define RX_MSDU_END_MESH_STA_MASK 0x0000000018000000 718 719 720 721 722 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 723 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 724 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 725 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 726 727 728 729 730 #define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 731 #define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 732 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 733 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 734 735 736 737 738 #define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 739 #define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 740 #define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 741 #define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 742 743 744 745 746 #define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 747 #define RX_MSDU_END_FSE_METADATA_LSB 32 748 #define RX_MSDU_END_FSE_METADATA_MSB 63 749 #define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 750 751 752 753 754 #define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 755 #define RX_MSDU_END_CCE_METADATA_LSB 0 756 #define RX_MSDU_END_CCE_METADATA_MSB 15 757 #define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff 758 759 760 761 762 #define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 763 #define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 764 #define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 765 #define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 766 767 768 769 770 #define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 771 #define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 772 #define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 773 #define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 774 775 776 777 778 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 779 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 780 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 781 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 782 783 784 785 786 #define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 787 #define RX_MSDU_END_FISA_TIMEOUT_LSB 41 788 #define RX_MSDU_END_FISA_TIMEOUT_MSB 41 789 #define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 790 791 792 793 794 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 795 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 796 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 797 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 798 799 800 801 802 #define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 803 #define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 804 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 805 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 806 807 808 809 810 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 811 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 812 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 813 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 814 815 816 817 818 #define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 819 #define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 820 #define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 821 #define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 822 823 824 825 826 #define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 827 #define RX_MSDU_END_CCE_MATCH_LSB 46 828 #define RX_MSDU_END_CCE_MATCH_MSB 46 829 #define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 830 831 832 833 834 #define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 835 #define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 836 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 837 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 838 839 840 841 842 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 843 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 844 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 845 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 846 847 848 849 850 #define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 851 #define RX_MSDU_END_KEY_ID_OCTET_LSB 0 852 #define RX_MSDU_END_KEY_ID_OCTET_MSB 7 853 #define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff 854 855 856 857 858 #define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 859 #define RX_MSDU_END_RESERVED_16A_LSB 8 860 #define RX_MSDU_END_RESERVED_16A_MSB 31 861 #define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 862 863 864 865 866 #define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 867 #define RX_MSDU_END_RESERVED_17A_LSB 32 868 #define RX_MSDU_END_RESERVED_17A_MSB 37 869 #define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 870 871 872 873 874 #define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 875 #define RX_MSDU_END_SERVICE_CODE_LSB 38 876 #define RX_MSDU_END_SERVICE_CODE_MSB 46 877 #define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 878 879 880 881 882 #define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 883 #define RX_MSDU_END_PRIORITY_VALID_LSB 47 884 #define RX_MSDU_END_PRIORITY_VALID_MSB 47 885 #define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 886 887 888 889 890 #define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 891 #define RX_MSDU_END_INTRA_BSS_LSB 48 892 #define RX_MSDU_END_INTRA_BSS_MSB 48 893 #define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 894 895 896 897 898 #define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 899 #define RX_MSDU_END_DEST_CHIP_ID_LSB 49 900 #define RX_MSDU_END_DEST_CHIP_ID_MSB 50 901 #define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 902 903 904 905 906 #define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 907 #define RX_MSDU_END_MULTICAST_ECHO_LSB 51 908 #define RX_MSDU_END_MULTICAST_ECHO_MSB 51 909 #define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 910 911 912 913 914 #define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 915 #define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 916 #define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 917 #define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 918 919 920 921 922 #define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 923 #define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 924 #define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 925 #define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 926 927 928 929 930 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 931 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 932 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 933 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 934 935 936 937 938 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_OFFSET 0x0000000000000040 939 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_LSB 55 940 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_MSB 55 941 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_MASK 0x0080000000000000 942 943 944 945 946 #define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 947 #define RX_MSDU_END_RESERVED_17B_LSB 56 948 #define RX_MSDU_END_RESERVED_17B_MSB 63 949 #define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 950 951 952 953 954 #define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 955 #define RX_MSDU_END_MSDU_LENGTH_LSB 0 956 #define RX_MSDU_END_MSDU_LENGTH_MSB 13 957 #define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff 958 959 960 961 962 #define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 963 #define RX_MSDU_END_STBC_LSB 14 964 #define RX_MSDU_END_STBC_MSB 14 965 #define RX_MSDU_END_STBC_MASK 0x0000000000004000 966 967 968 969 970 #define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 971 #define RX_MSDU_END_IPSEC_ESP_LSB 15 972 #define RX_MSDU_END_IPSEC_ESP_MSB 15 973 #define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 974 975 976 977 978 #define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 979 #define RX_MSDU_END_L3_OFFSET_LSB 16 980 #define RX_MSDU_END_L3_OFFSET_MSB 22 981 #define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 982 983 984 985 986 #define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 987 #define RX_MSDU_END_IPSEC_AH_LSB 23 988 #define RX_MSDU_END_IPSEC_AH_MSB 23 989 #define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 990 991 992 993 994 #define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 995 #define RX_MSDU_END_L4_OFFSET_LSB 24 996 #define RX_MSDU_END_L4_OFFSET_MSB 31 997 #define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 998 999 1000 1001 1002 #define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 1003 #define RX_MSDU_END_MSDU_NUMBER_LSB 32 1004 #define RX_MSDU_END_MSDU_NUMBER_MSB 39 1005 #define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 1006 1007 1008 1009 1010 #define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 1011 #define RX_MSDU_END_DECAP_FORMAT_LSB 40 1012 #define RX_MSDU_END_DECAP_FORMAT_MSB 41 1013 #define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 1014 1015 1016 1017 1018 #define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 1019 #define RX_MSDU_END_IPV4_PROTO_LSB 42 1020 #define RX_MSDU_END_IPV4_PROTO_MSB 42 1021 #define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 1022 1023 1024 1025 1026 #define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 1027 #define RX_MSDU_END_IPV6_PROTO_LSB 43 1028 #define RX_MSDU_END_IPV6_PROTO_MSB 43 1029 #define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 1030 1031 1032 1033 1034 #define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 1035 #define RX_MSDU_END_TCP_PROTO_LSB 44 1036 #define RX_MSDU_END_TCP_PROTO_MSB 44 1037 #define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 1038 1039 1040 1041 1042 #define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 1043 #define RX_MSDU_END_UDP_PROTO_LSB 45 1044 #define RX_MSDU_END_UDP_PROTO_MSB 45 1045 #define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 1046 1047 1048 1049 1050 #define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 1051 #define RX_MSDU_END_IP_FRAG_LSB 46 1052 #define RX_MSDU_END_IP_FRAG_MSB 46 1053 #define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 1054 1055 1056 1057 1058 #define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 1059 #define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 1060 #define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 1061 #define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 1062 1063 1064 1065 1066 #define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 1067 #define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 1068 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 1069 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 1070 1071 1072 1073 1074 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 1075 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 1076 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 1077 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 1078 1079 1080 1081 1082 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 1083 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 1084 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 1085 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 1086 1087 1088 1089 1090 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 1091 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 1092 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 1093 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 1094 1095 1096 1097 1098 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 1099 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 1100 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 1101 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 1102 1103 1104 1105 1106 #define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 1107 #define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 1108 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 1109 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 1110 1111 1112 1113 1114 #define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 1115 #define RX_MSDU_END_LDPC_LSB 55 1116 #define RX_MSDU_END_LDPC_MSB 55 1117 #define RX_MSDU_END_LDPC_MASK 0x0080000000000000 1118 1119 1120 1121 1122 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 1123 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 1124 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 1125 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 1126 1127 1128 1129 1130 #define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 1131 #define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 1132 #define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 1133 #define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff 1134 1135 1136 1137 1138 #define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 1139 #define RX_MSDU_END_VLAN_STAG_CI_LSB 16 1140 #define RX_MSDU_END_VLAN_STAG_CI_MSB 31 1141 #define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 1142 1143 1144 1145 1146 #define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 1147 #define RX_MSDU_END_PEER_META_DATA_LSB 32 1148 #define RX_MSDU_END_PEER_META_DATA_MSB 63 1149 #define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 1150 1151 1152 1153 1154 #define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 1155 #define RX_MSDU_END_USER_RSSI_LSB 0 1156 #define RX_MSDU_END_USER_RSSI_MSB 7 1157 #define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff 1158 1159 1160 1161 1162 #define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 1163 #define RX_MSDU_END_PKT_TYPE_LSB 8 1164 #define RX_MSDU_END_PKT_TYPE_MSB 11 1165 #define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 1166 1167 1168 1169 1170 #define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 1171 #define RX_MSDU_END_SGI_LSB 12 1172 #define RX_MSDU_END_SGI_MSB 13 1173 #define RX_MSDU_END_SGI_MASK 0x0000000000003000 1174 1175 1176 1177 1178 #define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 1179 #define RX_MSDU_END_RATE_MCS_LSB 14 1180 #define RX_MSDU_END_RATE_MCS_MSB 17 1181 #define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000 1182 1183 1184 1185 1186 #define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 1187 #define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 1188 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 1189 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000 1190 1191 1192 1193 1194 #define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 1195 #define RX_MSDU_END_RECEPTION_TYPE_LSB 21 1196 #define RX_MSDU_END_RECEPTION_TYPE_MSB 23 1197 #define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000 1198 1199 1200 1201 1202 #define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 1203 #define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 1204 #define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 1205 #define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007f000000 1206 1207 1208 1209 1210 #define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 1211 #define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 1212 #define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 1213 #define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 1214 1215 1216 1217 1218 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 1219 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 1220 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 1221 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 1222 1223 1224 1225 1226 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 1227 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 1228 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 1229 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff 1230 1231 1232 1233 1234 #define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 1235 #define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 1236 #define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 1237 #define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 1238 1239 1240 1241 1242 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 1243 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 1244 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 1245 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 1246 1247 1248 1249 1250 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 1251 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 1252 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 1253 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 1254 1255 1256 1257 1258 #define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 1259 #define RX_MSDU_END_RESERVED_28A_LSB 0 1260 #define RX_MSDU_END_RESERVED_28A_MSB 15 1261 #define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff 1262 1263 1264 1265 1266 #define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 1267 #define RX_MSDU_END_SA_15_0_LSB 16 1268 #define RX_MSDU_END_SA_15_0_MSB 31 1269 #define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 1270 1271 1272 1273 1274 #define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 1275 #define RX_MSDU_END_SA_47_16_LSB 32 1276 #define RX_MSDU_END_SA_47_16_MSB 63 1277 #define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 1278 1279 1280 1281 1282 #define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 1283 #define RX_MSDU_END_FIRST_MPDU_LSB 0 1284 #define RX_MSDU_END_FIRST_MPDU_MSB 0 1285 #define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 1286 1287 1288 1289 1290 #define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 1291 #define RX_MSDU_END_RESERVED_30A_LSB 1 1292 #define RX_MSDU_END_RESERVED_30A_MSB 1 1293 #define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 1294 1295 1296 1297 1298 #define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 1299 #define RX_MSDU_END_MCAST_BCAST_LSB 2 1300 #define RX_MSDU_END_MCAST_BCAST_MSB 2 1301 #define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 1302 1303 1304 1305 1306 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 1307 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 1308 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 1309 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 1310 1311 1312 1313 1314 #define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 1315 #define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 1316 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 1317 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 1318 1319 1320 1321 1322 #define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 1323 #define RX_MSDU_END_POWER_MGMT_LSB 5 1324 #define RX_MSDU_END_POWER_MGMT_MSB 5 1325 #define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 1326 1327 1328 1329 1330 #define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 1331 #define RX_MSDU_END_NON_QOS_LSB 6 1332 #define RX_MSDU_END_NON_QOS_MSB 6 1333 #define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 1334 1335 1336 1337 1338 #define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 1339 #define RX_MSDU_END_NULL_DATA_LSB 7 1340 #define RX_MSDU_END_NULL_DATA_MSB 7 1341 #define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 1342 1343 1344 1345 1346 #define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 1347 #define RX_MSDU_END_MGMT_TYPE_LSB 8 1348 #define RX_MSDU_END_MGMT_TYPE_MSB 8 1349 #define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 1350 1351 1352 1353 1354 #define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 1355 #define RX_MSDU_END_CTRL_TYPE_LSB 9 1356 #define RX_MSDU_END_CTRL_TYPE_MSB 9 1357 #define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 1358 1359 1360 1361 1362 #define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 1363 #define RX_MSDU_END_MORE_DATA_LSB 10 1364 #define RX_MSDU_END_MORE_DATA_MSB 10 1365 #define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 1366 1367 1368 1369 1370 #define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 1371 #define RX_MSDU_END_EOSP_LSB 11 1372 #define RX_MSDU_END_EOSP_MSB 11 1373 #define RX_MSDU_END_EOSP_MASK 0x0000000000000800 1374 1375 1376 1377 1378 #define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 1379 #define RX_MSDU_END_A_MSDU_ERROR_LSB 12 1380 #define RX_MSDU_END_A_MSDU_ERROR_MSB 12 1381 #define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 1382 1383 1384 1385 1386 #define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 1387 #define RX_MSDU_END_RESERVED_30B_LSB 13 1388 #define RX_MSDU_END_RESERVED_30B_MSB 13 1389 #define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 1390 1391 1392 1393 1394 #define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 1395 #define RX_MSDU_END_ORDER_LSB 14 1396 #define RX_MSDU_END_ORDER_MSB 14 1397 #define RX_MSDU_END_ORDER_MASK 0x0000000000004000 1398 1399 1400 1401 1402 #define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 1403 #define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 1404 #define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 1405 #define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 1406 1407 1408 1409 1410 #define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 1411 #define RX_MSDU_END_OVERFLOW_ERR_LSB 16 1412 #define RX_MSDU_END_OVERFLOW_ERR_MSB 16 1413 #define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 1414 1415 1416 1417 1418 #define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 1419 #define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 1420 #define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 1421 #define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 1422 1423 1424 1425 1426 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 1427 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 1428 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 1429 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 1430 1431 1432 1433 1434 #define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 1435 #define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 1436 #define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 1437 #define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 1438 1439 1440 1441 1442 #define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 1443 #define RX_MSDU_END_SA_IDX_INVALID_LSB 20 1444 #define RX_MSDU_END_SA_IDX_INVALID_MSB 20 1445 #define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 1446 1447 1448 1449 1450 #define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 1451 #define RX_MSDU_END_DA_IDX_INVALID_LSB 21 1452 #define RX_MSDU_END_DA_IDX_INVALID_MSB 21 1453 #define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 1454 1455 1456 1457 1458 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 1459 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 1460 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 1461 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 1462 1463 1464 1465 1466 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 1467 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 1468 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 1469 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 1470 1471 1472 1473 1474 #define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 1475 #define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 1476 #define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 1477 #define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 1478 1479 1480 1481 1482 #define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 1483 #define RX_MSDU_END_DIRECTED_LSB 25 1484 #define RX_MSDU_END_DIRECTED_MSB 25 1485 #define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 1486 1487 1488 1489 1490 #define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 1491 #define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 1492 #define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 1493 #define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 1494 1495 1496 1497 1498 #define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 1499 #define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 1500 #define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 1501 #define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 1502 1503 1504 1505 1506 #define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 1507 #define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 1508 #define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 1509 #define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 1510 1511 1512 1513 1514 #define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 1515 #define RX_MSDU_END_DECRYPT_ERR_LSB 29 1516 #define RX_MSDU_END_DECRYPT_ERR_MSB 29 1517 #define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 1518 1519 1520 1521 1522 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 1523 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 1524 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 1525 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 1526 1527 1528 1529 1530 #define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 1531 #define RX_MSDU_END_FCS_ERR_LSB 31 1532 #define RX_MSDU_END_FCS_ERR_MSB 31 1533 #define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 1534 1535 1536 1537 1538 #define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 1539 #define RX_MSDU_END_RESERVED_31A_LSB 32 1540 #define RX_MSDU_END_RESERVED_31A_MSB 41 1541 #define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 1542 1543 1544 1545 1546 #define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 1547 #define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 1548 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 1549 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 1550 1551 1552 1553 1554 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 1555 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 1556 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 1557 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 1558 1559 1560 1561 1562 #define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 1563 #define RX_MSDU_END_RESERVED_31B_LSB 46 1564 #define RX_MSDU_END_RESERVED_31B_MSB 62 1565 #define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000 1566 1567 1568 1569 1570 #define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 1571 #define RX_MSDU_END_MSDU_DONE_LSB 63 1572 #define RX_MSDU_END_MSDU_DONE_MSB 63 1573 #define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 1574 1575 1576 1577 #endif 1578