1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_MSDU_EXT_DESC_INFO_H_ 20 #define _RX_MSDU_EXT_DESC_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 25 26 27 struct rx_msdu_ext_desc_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t reo_destination_indication : 5, 30 service_code : 9, 31 priority_valid : 1, 32 data_offset : 12, 33 src_link_id : 3, 34 reserved_0a : 2; 35 #else 36 uint32_t reserved_0a : 2, 37 src_link_id : 3, 38 data_offset : 12, 39 priority_valid : 1, 40 service_code : 9, 41 reo_destination_indication : 5; 42 #endif 43 }; 44 45 46 47 48 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 49 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 50 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 51 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f 52 53 54 55 56 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 57 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 58 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 59 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 60 61 62 63 64 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 65 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 66 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 67 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 68 69 70 71 72 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 73 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 74 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 75 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 76 77 78 79 80 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 81 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 82 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 83 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 84 85 86 87 88 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 89 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 90 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 91 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 92 93 94 95 #endif 96