1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_PPDU_ACK_REPORT_H_ 20 #define _RX_PPDU_ACK_REPORT_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "ack_report.h" 25 #define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 26 27 #define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 28 29 30 struct rx_ppdu_ack_report { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct ack_report ack_report_details; 33 uint32_t tlv64_padding : 32; 34 #else 35 struct ack_report ack_report_details; 36 uint32_t tlv64_padding : 32; 37 #endif 38 }; 39 40 41 42 43 44 45 46 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 47 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 48 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 49 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f 50 51 52 53 54 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 55 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 56 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 57 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 58 59 60 61 62 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 63 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 64 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 65 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 66 67 68 69 70 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 71 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 72 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 73 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 74 75 76 77 78 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 79 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 80 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 81 #define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 82 83 84 85 86 #define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 87 #define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 88 #define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 89 #define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 90 91 92 93 #endif 94