1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_PPDU_END_USER_STATS_H_ 20 #define _RX_PPDU_END_USER_STATS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "rx_rxpcu_classification_overview.h" 25 #define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 26 27 #define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15 28 29 30 struct rx_ppdu_end_user_stats { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct rx_rxpcu_classification_overview rxpcu_classification_details; 33 uint32_t sta_full_aid : 13, 34 mcs : 4, 35 nss : 3, 36 expected_response_ack_or_ba : 1, 37 reserved_1a : 11; 38 uint32_t sw_peer_id : 16, 39 mpdu_cnt_fcs_err : 11, 40 sw2rxdma0_buf_source_used : 1, 41 fw2rxdma_pmac0_buf_source_used : 1, 42 sw2rxdma1_buf_source_used : 1, 43 sw2rxdma_exception_buf_source_used : 1, 44 fw2rxdma_pmac1_buf_source_used : 1; 45 uint32_t mpdu_cnt_fcs_ok : 11, 46 frame_control_info_valid : 1, 47 qos_control_info_valid : 1, 48 ht_control_info_valid : 1, 49 data_sequence_control_info_valid : 1, 50 ht_control_info_null_valid : 1, 51 rxdma2fw_pmac1_ring_used : 1, 52 rxdma2reo_ring_used : 1, 53 rxdma2fw_pmac0_ring_used : 1, 54 rxdma2sw_ring_used : 1, 55 rxdma_release_ring_used : 1, 56 ht_control_field_pkt_type : 4, 57 rxdma2reo_remote0_ring_used : 1, 58 rxdma2reo_remote1_ring_used : 1, 59 rxdma2reo_remote2_ring_used : 1, 60 rxdma2reo_remote3_ring_used : 1, 61 reserved_3b : 3; 62 uint32_t ast_index : 16, 63 frame_control_field : 16; 64 uint32_t first_data_seq_ctrl : 16, 65 qos_control_field : 16; 66 uint32_t ht_control_field : 32; 67 uint32_t fcs_ok_bitmap_31_0 : 32; 68 uint32_t fcs_ok_bitmap_63_32 : 32; 69 uint32_t udp_msdu_count : 16, 70 tcp_msdu_count : 16; 71 uint32_t other_msdu_count : 16, 72 tcp_ack_msdu_count : 16; 73 uint32_t sw_response_reference_ptr : 32; 74 uint32_t received_qos_data_tid_bitmap : 16, 75 received_qos_data_tid_eosp_bitmap : 16; 76 uint32_t qosctrl_15_8_tid0 : 8, 77 qosctrl_15_8_tid1 : 8, 78 qosctrl_15_8_tid2 : 8, 79 qosctrl_15_8_tid3 : 8; 80 uint32_t qosctrl_15_8_tid4 : 8, 81 qosctrl_15_8_tid5 : 8, 82 qosctrl_15_8_tid6 : 8, 83 qosctrl_15_8_tid7 : 8; 84 uint32_t qosctrl_15_8_tid8 : 8, 85 qosctrl_15_8_tid9 : 8, 86 qosctrl_15_8_tid10 : 8, 87 qosctrl_15_8_tid11 : 8; 88 uint32_t qosctrl_15_8_tid12 : 8, 89 qosctrl_15_8_tid13 : 8, 90 qosctrl_15_8_tid14 : 8, 91 qosctrl_15_8_tid15 : 8; 92 uint32_t mpdu_ok_byte_count : 25, 93 ampdu_delim_ok_count_6_0 : 7; 94 uint32_t ampdu_delim_err_count : 25, 95 ampdu_delim_ok_count_13_7 : 7; 96 uint32_t mpdu_err_byte_count : 25, 97 ampdu_delim_ok_count_20_14 : 7; 98 uint32_t non_consecutive_delimiter_err : 16, 99 retried_msdu_count : 16; 100 uint32_t ht_control_null_field : 32; 101 uint32_t sw_response_reference_ptr_ext : 32; 102 uint32_t corrupted_due_to_fifo_delay : 1, 103 frame_control_info_null_valid : 1, 104 frame_control_field_null : 16, 105 retried_mpdu_count : 11, 106 reserved_23a : 3; 107 uint32_t rxpcu_mpdu_filter_in_category : 2, 108 sw_frame_group_id : 7, 109 reserved_24a : 4, 110 frame_control_info_mgmt_ctrl_valid : 1, 111 mac_addr_ad2_valid : 1, 112 mcast_bcast : 1, 113 frame_control_field_mgmt_ctrl : 16; 114 uint32_t user_ppdu_len : 24, 115 reserved_25a : 8; 116 uint32_t mac_addr_ad2_31_0 : 32; 117 uint32_t mac_addr_ad2_47_32 : 16, 118 amsdu_msdu_count : 16; 119 uint32_t non_amsdu_msdu_count : 16, 120 ucast_msdu_count : 16; 121 uint32_t bcast_msdu_count : 16, 122 mcast_bcast_msdu_count : 16; 123 #else 124 struct rx_rxpcu_classification_overview rxpcu_classification_details; 125 uint32_t reserved_1a : 11, 126 expected_response_ack_or_ba : 1, 127 nss : 3, 128 mcs : 4, 129 sta_full_aid : 13; 130 uint32_t fw2rxdma_pmac1_buf_source_used : 1, 131 sw2rxdma_exception_buf_source_used : 1, 132 sw2rxdma1_buf_source_used : 1, 133 fw2rxdma_pmac0_buf_source_used : 1, 134 sw2rxdma0_buf_source_used : 1, 135 mpdu_cnt_fcs_err : 11, 136 sw_peer_id : 16; 137 uint32_t reserved_3b : 3, 138 rxdma2reo_remote3_ring_used : 1, 139 rxdma2reo_remote2_ring_used : 1, 140 rxdma2reo_remote1_ring_used : 1, 141 rxdma2reo_remote0_ring_used : 1, 142 ht_control_field_pkt_type : 4, 143 rxdma_release_ring_used : 1, 144 rxdma2sw_ring_used : 1, 145 rxdma2fw_pmac0_ring_used : 1, 146 rxdma2reo_ring_used : 1, 147 rxdma2fw_pmac1_ring_used : 1, 148 ht_control_info_null_valid : 1, 149 data_sequence_control_info_valid : 1, 150 ht_control_info_valid : 1, 151 qos_control_info_valid : 1, 152 frame_control_info_valid : 1, 153 mpdu_cnt_fcs_ok : 11; 154 uint32_t frame_control_field : 16, 155 ast_index : 16; 156 uint32_t qos_control_field : 16, 157 first_data_seq_ctrl : 16; 158 uint32_t ht_control_field : 32; 159 uint32_t fcs_ok_bitmap_31_0 : 32; 160 uint32_t fcs_ok_bitmap_63_32 : 32; 161 uint32_t tcp_msdu_count : 16, 162 udp_msdu_count : 16; 163 uint32_t tcp_ack_msdu_count : 16, 164 other_msdu_count : 16; 165 uint32_t sw_response_reference_ptr : 32; 166 uint32_t received_qos_data_tid_eosp_bitmap : 16, 167 received_qos_data_tid_bitmap : 16; 168 uint32_t qosctrl_15_8_tid3 : 8, 169 qosctrl_15_8_tid2 : 8, 170 qosctrl_15_8_tid1 : 8, 171 qosctrl_15_8_tid0 : 8; 172 uint32_t qosctrl_15_8_tid7 : 8, 173 qosctrl_15_8_tid6 : 8, 174 qosctrl_15_8_tid5 : 8, 175 qosctrl_15_8_tid4 : 8; 176 uint32_t qosctrl_15_8_tid11 : 8, 177 qosctrl_15_8_tid10 : 8, 178 qosctrl_15_8_tid9 : 8, 179 qosctrl_15_8_tid8 : 8; 180 uint32_t qosctrl_15_8_tid15 : 8, 181 qosctrl_15_8_tid14 : 8, 182 qosctrl_15_8_tid13 : 8, 183 qosctrl_15_8_tid12 : 8; 184 uint32_t ampdu_delim_ok_count_6_0 : 7, 185 mpdu_ok_byte_count : 25; 186 uint32_t ampdu_delim_ok_count_13_7 : 7, 187 ampdu_delim_err_count : 25; 188 uint32_t ampdu_delim_ok_count_20_14 : 7, 189 mpdu_err_byte_count : 25; 190 uint32_t retried_msdu_count : 16, 191 non_consecutive_delimiter_err : 16; 192 uint32_t ht_control_null_field : 32; 193 uint32_t sw_response_reference_ptr_ext : 32; 194 uint32_t reserved_23a : 3, 195 retried_mpdu_count : 11, 196 frame_control_field_null : 16, 197 frame_control_info_null_valid : 1, 198 corrupted_due_to_fifo_delay : 1; 199 uint32_t frame_control_field_mgmt_ctrl : 16, 200 mcast_bcast : 1, 201 mac_addr_ad2_valid : 1, 202 frame_control_info_mgmt_ctrl_valid : 1, 203 reserved_24a : 4, 204 sw_frame_group_id : 7, 205 rxpcu_mpdu_filter_in_category : 2; 206 uint32_t reserved_25a : 8, 207 user_ppdu_len : 24; 208 uint32_t mac_addr_ad2_31_0 : 32; 209 uint32_t amsdu_msdu_count : 16, 210 mac_addr_ad2_47_32 : 16; 211 uint32_t ucast_msdu_count : 16, 212 non_amsdu_msdu_count : 16; 213 uint32_t mcast_bcast_msdu_count : 16, 214 bcast_msdu_count : 16; 215 #endif 216 }; 217 218 219 220 221 222 223 224 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 225 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 226 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 227 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 228 229 230 231 232 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 233 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 234 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 235 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 236 237 238 239 240 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 241 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 242 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 243 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 244 245 246 247 248 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 249 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 250 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 251 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 252 253 254 255 256 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 257 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 258 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 259 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 260 261 262 263 264 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 265 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 266 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 267 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 268 269 270 271 272 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 273 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 274 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 275 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 276 277 278 279 280 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 281 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 282 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 283 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 284 285 286 287 288 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 289 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 290 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 291 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 292 293 294 295 296 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 297 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 298 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 299 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 300 301 302 303 304 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 305 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 306 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 307 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 308 309 310 311 312 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 313 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 314 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 315 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 316 317 318 319 320 #define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 321 #define RX_PPDU_END_USER_STATS_MCS_LSB 45 322 #define RX_PPDU_END_USER_STATS_MCS_MSB 48 323 #define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e00000000000 324 325 326 327 328 #define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 329 #define RX_PPDU_END_USER_STATS_NSS_LSB 49 330 #define RX_PPDU_END_USER_STATS_NSS_MSB 51 331 #define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e000000000000 332 333 334 335 336 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 337 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 52 338 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 52 339 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0010000000000000 340 341 342 343 344 #define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 345 #define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 53 346 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 347 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe0000000000000 348 349 350 351 352 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 353 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 354 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 355 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff 356 357 358 359 360 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 361 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 362 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 363 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 364 365 366 367 368 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 369 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 370 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 371 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 372 373 374 375 376 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 377 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 378 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 379 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x0000000010000000 380 381 382 383 384 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 385 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 386 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 387 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 388 389 390 391 392 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x0000000000000008 393 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 394 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 395 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x0000000040000000 396 397 398 399 400 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 401 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 402 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 403 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x0000000080000000 404 405 406 407 408 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 409 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 410 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 411 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 412 413 414 415 416 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 417 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 418 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 419 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 420 421 422 423 424 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 425 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 426 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 427 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 428 429 430 431 432 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 433 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 434 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 435 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 436 437 438 439 440 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 441 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 442 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 443 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 444 445 446 447 448 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 449 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 450 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 451 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 452 453 454 455 456 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000000000008 457 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 48 458 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 48 459 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x0001000000000000 460 461 462 463 464 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000000000008 465 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 49 466 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 49 467 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x0002000000000000 468 469 470 471 472 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000000000008 473 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 50 474 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 50 475 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x0004000000000000 476 477 478 479 480 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000000000008 481 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 51 482 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 51 483 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x0008000000000000 484 485 486 487 488 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000000000008 489 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 52 490 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 52 491 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x0010000000000000 492 493 494 495 496 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 497 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 498 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 499 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 500 501 502 503 504 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000000000008 505 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 57 506 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 57 507 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x0200000000000000 508 509 510 511 512 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000000000008 513 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 58 514 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 58 515 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x0400000000000000 516 517 518 519 520 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE2_RING_USED_OFFSET 0x0000000000000008 521 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE2_RING_USED_LSB 59 522 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE2_RING_USED_MSB 59 523 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE2_RING_USED_MASK 0x0800000000000000 524 525 526 527 528 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE3_RING_USED_OFFSET 0x0000000000000008 529 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE3_RING_USED_LSB 60 530 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE3_RING_USED_MSB 60 531 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE3_RING_USED_MASK 0x1000000000000000 532 533 534 535 536 #define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 537 #define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 61 538 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 539 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xe000000000000000 540 541 542 543 544 #define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 545 #define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 546 #define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 547 #define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff 548 549 550 551 552 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 553 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 554 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 555 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 556 557 558 559 560 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 561 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 562 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 563 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 564 565 566 567 568 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 569 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 570 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 571 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 572 573 574 575 576 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 577 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 578 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 579 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff 580 581 582 583 584 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 585 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 586 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 587 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 588 589 590 591 592 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 593 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 594 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 595 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff 596 597 598 599 600 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 601 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 602 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 603 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 604 605 606 607 608 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 609 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 610 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 611 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 612 613 614 615 616 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 617 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 618 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 619 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff 620 621 622 623 624 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 625 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 626 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 627 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 628 629 630 631 632 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 633 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 634 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 635 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 636 637 638 639 640 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 641 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 642 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 643 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff 644 645 646 647 648 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 649 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 650 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 651 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 652 653 654 655 656 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 657 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 658 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 659 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 660 661 662 663 664 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 665 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 666 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 667 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 668 669 670 671 672 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 673 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 674 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 675 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 676 677 678 679 680 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 681 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 682 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 683 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 684 685 686 687 688 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 689 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 690 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 691 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff 692 693 694 695 696 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 697 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 698 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 699 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 700 701 702 703 704 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 705 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 706 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 707 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 708 709 710 711 712 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 713 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 714 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 715 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 716 717 718 719 720 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 721 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 722 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 723 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 724 725 726 727 728 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 729 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 730 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 731 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 732 733 734 735 736 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 737 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 738 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 739 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 740 741 742 743 744 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 745 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 746 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 747 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 748 749 750 751 752 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 753 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 754 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 755 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff 756 757 758 759 760 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 761 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 762 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 763 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 764 765 766 767 768 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 769 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 770 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 771 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 772 773 774 775 776 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 777 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 778 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 779 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 780 781 782 783 784 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 785 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 786 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 787 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 788 789 790 791 792 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 793 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 794 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 795 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 796 797 798 799 800 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 801 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 802 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 803 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff 804 805 806 807 808 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 809 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 810 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 811 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 812 813 814 815 816 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 817 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 818 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 819 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 820 821 822 823 824 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 825 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 826 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 827 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 828 829 830 831 832 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 833 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 834 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 835 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff 836 837 838 839 840 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 841 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 842 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 843 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 844 845 846 847 848 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 849 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 850 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 851 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 852 853 854 855 856 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 857 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 858 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 859 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff 860 861 862 863 864 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 865 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 866 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 867 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 868 869 870 871 872 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 873 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 874 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 875 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 876 877 878 879 880 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 881 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 882 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 883 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 884 885 886 887 888 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 889 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 890 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 891 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 892 893 894 895 896 #define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 897 #define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 898 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 899 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 900 901 902 903 904 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000060 905 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 906 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 907 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 908 909 910 911 912 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000060 913 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 914 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 915 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 916 917 918 919 920 #define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x0000000000000060 921 #define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 922 #define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 923 #define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x0000000000001e00 924 925 926 927 928 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x0000000000000060 929 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 930 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 931 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x0000000000002000 932 933 934 935 936 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000060 937 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 938 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 939 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x0000000000004000 940 941 942 943 944 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x0000000000000060 945 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 946 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 947 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x0000000000008000 948 949 950 951 952 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x0000000000000060 953 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 954 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 955 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0x00000000ffff0000 956 957 958 959 960 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x0000000000000060 961 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 32 962 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 55 963 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff00000000 964 965 966 967 968 #define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x0000000000000060 969 #define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 56 970 #define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 63 971 #define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff00000000000000 972 973 974 975 976 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x0000000000000068 977 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 978 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 979 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0x00000000ffffffff 980 981 982 983 984 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000000000000068 985 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 32 986 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 47 987 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff00000000 988 989 990 991 992 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000068 993 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 48 994 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 63 995 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff000000000000 996 997 998 999 1000 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000070 1001 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 1002 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 1003 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x000000000000ffff 1004 1005 1006 1007 1008 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x0000000000000070 1009 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 1010 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 1011 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000 1012 1013 1014 1015 1016 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 1017 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32 1018 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47 1019 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000 1020 1021 1022 1023 1024 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 1025 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 48 1026 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 63 1027 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff000000000000 1028 1029 1030 1031 #endif 1032