1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_REO_QUEUE_H_ 20 #define _RX_REO_QUEUE_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_descriptor_header.h" 25 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 26 27 28 struct rx_reo_queue { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_descriptor_header descriptor_header; 31 uint32_t receive_queue_number : 16, 32 reserved_1b : 16; 33 uint32_t vld : 1, 34 associated_link_descriptor_counter : 2, 35 disable_duplicate_detection : 1, 36 soft_reorder_enable : 1, 37 ac : 2, 38 bar : 1, 39 rty : 1, 40 chk_2k_mode : 1, 41 oor_mode : 1, 42 ba_window_size : 10, 43 pn_check_needed : 1, 44 pn_shall_be_even : 1, 45 pn_shall_be_uneven : 1, 46 pn_handling_enable : 1, 47 pn_size : 2, 48 ignore_ampdu_flag : 1, 49 reserved_2b : 4; 50 uint32_t svld : 1, 51 ssn : 12, 52 current_index : 10, 53 seq_2k_error_detected_flag : 1, 54 pn_error_detected_flag : 1, 55 reserved_3a : 6, 56 pn_valid : 1; 57 uint32_t pn_31_0 : 32; 58 uint32_t pn_63_32 : 32; 59 uint32_t pn_95_64 : 32; 60 uint32_t pn_127_96 : 32; 61 uint32_t last_rx_enqueue_timestamp : 32; 62 uint32_t last_rx_dequeue_timestamp : 32; 63 uint32_t ptr_to_next_aging_queue_31_0 : 32; 64 uint32_t ptr_to_next_aging_queue_39_32 : 8, 65 reserved_11a : 24; 66 uint32_t ptr_to_previous_aging_queue_31_0 : 32; 67 uint32_t ptr_to_previous_aging_queue_39_32 : 8, 68 statistics_counter_index : 6, 69 reserved_13a : 18; 70 uint32_t rx_bitmap_31_0 : 32; 71 uint32_t rx_bitmap_63_32 : 32; 72 uint32_t rx_bitmap_95_64 : 32; 73 uint32_t rx_bitmap_127_96 : 32; 74 uint32_t rx_bitmap_159_128 : 32; 75 uint32_t rx_bitmap_191_160 : 32; 76 uint32_t rx_bitmap_223_192 : 32; 77 uint32_t rx_bitmap_255_224 : 32; 78 uint32_t rx_bitmap_287_256 : 32; 79 uint32_t current_mpdu_count : 7, 80 current_msdu_count : 25; 81 uint32_t last_sn_reg_index : 4, 82 timeout_count : 6, 83 forward_due_to_bar_count : 6, 84 duplicate_count : 16; 85 uint32_t frames_in_order_count : 24, 86 bar_received_count : 8; 87 uint32_t mpdu_frames_processed_count : 32; 88 uint32_t msdu_frames_processed_count : 32; 89 uint32_t total_processed_byte_count : 32; 90 uint32_t late_receive_mpdu_count : 12, 91 window_jump_2k : 4, 92 hole_count : 16; 93 uint32_t aging_drop_mpdu_count : 16, 94 aging_drop_interval : 8, 95 reserved_30 : 8; 96 uint32_t reserved_31 : 32; 97 #else 98 struct uniform_descriptor_header descriptor_header; 99 uint32_t reserved_1b : 16, 100 receive_queue_number : 16; 101 uint32_t reserved_2b : 4, 102 ignore_ampdu_flag : 1, 103 pn_size : 2, 104 pn_handling_enable : 1, 105 pn_shall_be_uneven : 1, 106 pn_shall_be_even : 1, 107 pn_check_needed : 1, 108 ba_window_size : 10, 109 oor_mode : 1, 110 chk_2k_mode : 1, 111 rty : 1, 112 bar : 1, 113 ac : 2, 114 soft_reorder_enable : 1, 115 disable_duplicate_detection : 1, 116 associated_link_descriptor_counter : 2, 117 vld : 1; 118 uint32_t pn_valid : 1, 119 reserved_3a : 6, 120 pn_error_detected_flag : 1, 121 seq_2k_error_detected_flag : 1, 122 current_index : 10, 123 ssn : 12, 124 svld : 1; 125 uint32_t pn_31_0 : 32; 126 uint32_t pn_63_32 : 32; 127 uint32_t pn_95_64 : 32; 128 uint32_t pn_127_96 : 32; 129 uint32_t last_rx_enqueue_timestamp : 32; 130 uint32_t last_rx_dequeue_timestamp : 32; 131 uint32_t ptr_to_next_aging_queue_31_0 : 32; 132 uint32_t reserved_11a : 24, 133 ptr_to_next_aging_queue_39_32 : 8; 134 uint32_t ptr_to_previous_aging_queue_31_0 : 32; 135 uint32_t reserved_13a : 18, 136 statistics_counter_index : 6, 137 ptr_to_previous_aging_queue_39_32 : 8; 138 uint32_t rx_bitmap_31_0 : 32; 139 uint32_t rx_bitmap_63_32 : 32; 140 uint32_t rx_bitmap_95_64 : 32; 141 uint32_t rx_bitmap_127_96 : 32; 142 uint32_t rx_bitmap_159_128 : 32; 143 uint32_t rx_bitmap_191_160 : 32; 144 uint32_t rx_bitmap_223_192 : 32; 145 uint32_t rx_bitmap_255_224 : 32; 146 uint32_t rx_bitmap_287_256 : 32; 147 uint32_t current_msdu_count : 25, 148 current_mpdu_count : 7; 149 uint32_t duplicate_count : 16, 150 forward_due_to_bar_count : 6, 151 timeout_count : 6, 152 last_sn_reg_index : 4; 153 uint32_t bar_received_count : 8, 154 frames_in_order_count : 24; 155 uint32_t mpdu_frames_processed_count : 32; 156 uint32_t msdu_frames_processed_count : 32; 157 uint32_t total_processed_byte_count : 32; 158 uint32_t hole_count : 16, 159 window_jump_2k : 4, 160 late_receive_mpdu_count : 12; 161 uint32_t reserved_30 : 8, 162 aging_drop_interval : 8, 163 aging_drop_mpdu_count : 16; 164 uint32_t reserved_31 : 32; 165 #endif 166 }; 167 168 169 170 171 172 173 174 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 175 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 176 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 177 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 178 179 180 181 182 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 183 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 184 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 185 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 186 187 188 189 190 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 191 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 192 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 193 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 194 195 196 197 198 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 199 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 200 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 201 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 202 203 204 205 206 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 207 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 208 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 209 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 210 211 212 213 214 #define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 215 #define RX_REO_QUEUE_RESERVED_1B_LSB 16 216 #define RX_REO_QUEUE_RESERVED_1B_MSB 31 217 #define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 218 219 220 221 222 #define RX_REO_QUEUE_VLD_OFFSET 0x00000008 223 #define RX_REO_QUEUE_VLD_LSB 0 224 #define RX_REO_QUEUE_VLD_MSB 0 225 #define RX_REO_QUEUE_VLD_MASK 0x00000001 226 227 228 229 230 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 231 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 232 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 233 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 234 235 236 237 238 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 239 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 240 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 241 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 242 243 244 245 246 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 247 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 248 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 249 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 250 251 252 253 254 #define RX_REO_QUEUE_AC_OFFSET 0x00000008 255 #define RX_REO_QUEUE_AC_LSB 5 256 #define RX_REO_QUEUE_AC_MSB 6 257 #define RX_REO_QUEUE_AC_MASK 0x00000060 258 259 260 261 262 #define RX_REO_QUEUE_BAR_OFFSET 0x00000008 263 #define RX_REO_QUEUE_BAR_LSB 7 264 #define RX_REO_QUEUE_BAR_MSB 7 265 #define RX_REO_QUEUE_BAR_MASK 0x00000080 266 267 268 269 270 #define RX_REO_QUEUE_RTY_OFFSET 0x00000008 271 #define RX_REO_QUEUE_RTY_LSB 8 272 #define RX_REO_QUEUE_RTY_MSB 8 273 #define RX_REO_QUEUE_RTY_MASK 0x00000100 274 275 276 277 278 #define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 279 #define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 280 #define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 281 #define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 282 283 284 285 286 #define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 287 #define RX_REO_QUEUE_OOR_MODE_LSB 10 288 #define RX_REO_QUEUE_OOR_MODE_MSB 10 289 #define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 290 291 292 293 294 #define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 295 #define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 296 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 297 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 298 299 300 301 302 #define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 303 #define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 304 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 305 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 306 307 308 309 310 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 311 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 312 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 313 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 314 315 316 317 318 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 319 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 320 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 321 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 322 323 324 325 326 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 327 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 328 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 329 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 330 331 332 333 334 #define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 335 #define RX_REO_QUEUE_PN_SIZE_LSB 25 336 #define RX_REO_QUEUE_PN_SIZE_MSB 26 337 #define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 338 339 340 341 342 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 343 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 344 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 345 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 346 347 348 349 350 #define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 351 #define RX_REO_QUEUE_RESERVED_2B_LSB 28 352 #define RX_REO_QUEUE_RESERVED_2B_MSB 31 353 #define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 354 355 356 357 358 #define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c 359 #define RX_REO_QUEUE_SVLD_LSB 0 360 #define RX_REO_QUEUE_SVLD_MSB 0 361 #define RX_REO_QUEUE_SVLD_MASK 0x00000001 362 363 364 365 366 #define RX_REO_QUEUE_SSN_OFFSET 0x0000000c 367 #define RX_REO_QUEUE_SSN_LSB 1 368 #define RX_REO_QUEUE_SSN_MSB 12 369 #define RX_REO_QUEUE_SSN_MASK 0x00001ffe 370 371 372 373 374 #define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c 375 #define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 376 #define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 377 #define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 378 379 380 381 382 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 383 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 384 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 385 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 386 387 388 389 390 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 391 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 392 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 393 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 394 395 396 397 398 #define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c 399 #define RX_REO_QUEUE_RESERVED_3A_LSB 25 400 #define RX_REO_QUEUE_RESERVED_3A_MSB 30 401 #define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 402 403 404 405 406 #define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c 407 #define RX_REO_QUEUE_PN_VALID_LSB 31 408 #define RX_REO_QUEUE_PN_VALID_MSB 31 409 #define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 410 411 412 413 414 #define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 415 #define RX_REO_QUEUE_PN_31_0_LSB 0 416 #define RX_REO_QUEUE_PN_31_0_MSB 31 417 #define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff 418 419 420 421 422 #define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 423 #define RX_REO_QUEUE_PN_63_32_LSB 0 424 #define RX_REO_QUEUE_PN_63_32_MSB 31 425 #define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff 426 427 428 429 430 #define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 431 #define RX_REO_QUEUE_PN_95_64_LSB 0 432 #define RX_REO_QUEUE_PN_95_64_MSB 31 433 #define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff 434 435 436 437 438 #define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c 439 #define RX_REO_QUEUE_PN_127_96_LSB 0 440 #define RX_REO_QUEUE_PN_127_96_MSB 31 441 #define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff 442 443 444 445 446 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 447 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 448 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 449 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 450 451 452 453 454 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 455 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 456 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 457 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 458 459 460 461 462 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 463 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 464 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 465 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 466 467 468 469 470 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 471 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 472 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 473 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 474 475 476 477 478 #define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c 479 #define RX_REO_QUEUE_RESERVED_11A_LSB 8 480 #define RX_REO_QUEUE_RESERVED_11A_MSB 31 481 #define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 482 483 484 485 486 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 487 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 488 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 489 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 490 491 492 493 494 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 495 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 496 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 497 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 498 499 500 501 502 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 503 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 504 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 505 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 506 507 508 509 510 #define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 511 #define RX_REO_QUEUE_RESERVED_13A_LSB 14 512 #define RX_REO_QUEUE_RESERVED_13A_MSB 31 513 #define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 514 515 516 517 518 #define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 519 #define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 520 #define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 521 #define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff 522 523 524 525 526 #define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c 527 #define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 528 #define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 529 #define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff 530 531 532 533 534 #define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 535 #define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 536 #define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 537 #define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff 538 539 540 541 542 #define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 543 #define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 544 #define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 545 #define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff 546 547 548 549 550 #define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 551 #define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 552 #define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 553 #define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff 554 555 556 557 558 #define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c 559 #define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 560 #define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 561 #define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff 562 563 564 565 566 #define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 567 #define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 568 #define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 569 #define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff 570 571 572 573 574 #define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 575 #define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 576 #define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 577 #define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff 578 579 580 581 582 #define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 583 #define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 584 #define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 585 #define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff 586 587 588 589 590 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c 591 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 592 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 593 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f 594 595 596 597 598 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c 599 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 600 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 601 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 602 603 604 605 606 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 607 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 608 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 609 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f 610 611 612 613 614 #define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 615 #define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 616 #define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 617 #define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 618 619 620 621 622 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 623 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 624 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 625 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 626 627 628 629 630 #define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 631 #define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 632 #define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 633 #define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 634 635 636 637 638 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 639 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 640 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 641 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 642 643 644 645 646 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 647 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 648 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 649 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 650 651 652 653 654 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 655 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 656 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 657 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 658 659 660 661 662 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c 663 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 664 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 665 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 666 667 668 669 670 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 671 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 672 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 673 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 674 675 676 677 678 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 679 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 680 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 681 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 682 683 684 685 686 #define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 687 #define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 688 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 689 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 690 691 692 693 694 #define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 695 #define RX_REO_QUEUE_HOLE_COUNT_LSB 16 696 #define RX_REO_QUEUE_HOLE_COUNT_MSB 31 697 #define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 698 699 700 701 702 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 703 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 704 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 705 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff 706 707 708 709 710 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 711 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 712 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 713 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 714 715 716 717 718 #define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 719 #define RX_REO_QUEUE_RESERVED_30_LSB 24 720 #define RX_REO_QUEUE_RESERVED_30_MSB 31 721 #define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 722 723 724 725 726 #define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c 727 #define RX_REO_QUEUE_RESERVED_31_LSB 0 728 #define RX_REO_QUEUE_RESERVED_31_MSB 31 729 #define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff 730 731 732 733 #endif 734