1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_REO_QUEUE_1K_H_ 20 #define _RX_REO_QUEUE_1K_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_descriptor_header.h" 25 #define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 26 27 28 struct rx_reo_queue_1k { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_descriptor_header descriptor_header; 31 uint32_t rx_bitmap_319_288 : 32; 32 uint32_t rx_bitmap_351_320 : 32; 33 uint32_t rx_bitmap_383_352 : 32; 34 uint32_t rx_bitmap_415_384 : 32; 35 uint32_t rx_bitmap_447_416 : 32; 36 uint32_t rx_bitmap_479_448 : 32; 37 uint32_t rx_bitmap_511_480 : 32; 38 uint32_t rx_bitmap_543_512 : 32; 39 uint32_t rx_bitmap_575_544 : 32; 40 uint32_t rx_bitmap_607_576 : 32; 41 uint32_t rx_bitmap_639_608 : 32; 42 uint32_t rx_bitmap_671_640 : 32; 43 uint32_t rx_bitmap_703_672 : 32; 44 uint32_t rx_bitmap_735_704 : 32; 45 uint32_t rx_bitmap_767_736 : 32; 46 uint32_t rx_bitmap_799_768 : 32; 47 uint32_t rx_bitmap_831_800 : 32; 48 uint32_t rx_bitmap_863_832 : 32; 49 uint32_t rx_bitmap_895_864 : 32; 50 uint32_t rx_bitmap_927_896 : 32; 51 uint32_t rx_bitmap_959_928 : 32; 52 uint32_t rx_bitmap_991_960 : 32; 53 uint32_t rx_bitmap_1023_992 : 32; 54 uint32_t reserved_24 : 32; 55 uint32_t reserved_25 : 32; 56 uint32_t reserved_26 : 32; 57 uint32_t reserved_27 : 32; 58 uint32_t reserved_28 : 32; 59 uint32_t reserved_29 : 32; 60 uint32_t reserved_30 : 32; 61 uint32_t reserved_31 : 32; 62 #else 63 struct uniform_descriptor_header descriptor_header; 64 uint32_t rx_bitmap_319_288 : 32; 65 uint32_t rx_bitmap_351_320 : 32; 66 uint32_t rx_bitmap_383_352 : 32; 67 uint32_t rx_bitmap_415_384 : 32; 68 uint32_t rx_bitmap_447_416 : 32; 69 uint32_t rx_bitmap_479_448 : 32; 70 uint32_t rx_bitmap_511_480 : 32; 71 uint32_t rx_bitmap_543_512 : 32; 72 uint32_t rx_bitmap_575_544 : 32; 73 uint32_t rx_bitmap_607_576 : 32; 74 uint32_t rx_bitmap_639_608 : 32; 75 uint32_t rx_bitmap_671_640 : 32; 76 uint32_t rx_bitmap_703_672 : 32; 77 uint32_t rx_bitmap_735_704 : 32; 78 uint32_t rx_bitmap_767_736 : 32; 79 uint32_t rx_bitmap_799_768 : 32; 80 uint32_t rx_bitmap_831_800 : 32; 81 uint32_t rx_bitmap_863_832 : 32; 82 uint32_t rx_bitmap_895_864 : 32; 83 uint32_t rx_bitmap_927_896 : 32; 84 uint32_t rx_bitmap_959_928 : 32; 85 uint32_t rx_bitmap_991_960 : 32; 86 uint32_t rx_bitmap_1023_992 : 32; 87 uint32_t reserved_24 : 32; 88 uint32_t reserved_25 : 32; 89 uint32_t reserved_26 : 32; 90 uint32_t reserved_27 : 32; 91 uint32_t reserved_28 : 32; 92 uint32_t reserved_29 : 32; 93 uint32_t reserved_30 : 32; 94 uint32_t reserved_31 : 32; 95 #endif 96 }; 97 98 99 100 101 102 103 104 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 105 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 106 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 107 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 108 109 110 111 112 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 113 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 114 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 115 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 116 117 118 119 120 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 121 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 122 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 123 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 124 125 126 127 128 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 129 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 130 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 131 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 132 133 134 135 136 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 137 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 138 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 139 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff 140 141 142 143 144 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 145 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 146 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 147 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff 148 149 150 151 152 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c 153 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 154 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 155 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff 156 157 158 159 160 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 161 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 162 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 163 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff 164 165 166 167 168 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 169 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 170 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 171 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff 172 173 174 175 176 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 177 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 178 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 179 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff 180 181 182 183 184 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c 185 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 186 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 187 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff 188 189 190 191 192 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 193 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 194 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 195 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff 196 197 198 199 200 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 201 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 202 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 203 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff 204 205 206 207 208 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 209 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 210 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 211 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff 212 213 214 215 216 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c 217 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 218 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 219 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff 220 221 222 223 224 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 225 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 226 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 227 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff 228 229 230 231 232 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 233 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 234 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 235 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff 236 237 238 239 240 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 241 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 242 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 243 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff 244 245 246 247 248 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c 249 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 250 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 251 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff 252 253 254 255 256 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 257 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 258 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 259 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff 260 261 262 263 264 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 265 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 266 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 267 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff 268 269 270 271 272 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 273 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 274 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 275 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff 276 277 278 279 280 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c 281 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 282 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 283 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff 284 285 286 287 288 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 289 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 290 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 291 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff 292 293 294 295 296 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 297 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 298 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 299 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff 300 301 302 303 304 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 305 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 306 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 307 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff 308 309 310 311 312 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c 313 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 314 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 315 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff 316 317 318 319 320 #define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 321 #define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 322 #define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 323 #define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff 324 325 326 327 328 #define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 329 #define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 330 #define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 331 #define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff 332 333 334 335 336 #define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 337 #define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 338 #define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 339 #define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff 340 341 342 343 344 #define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c 345 #define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 346 #define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 347 #define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff 348 349 350 351 352 #define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 353 #define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 354 #define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 355 #define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff 356 357 358 359 360 #define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 361 #define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 362 #define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 363 #define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff 364 365 366 367 368 #define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 369 #define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 370 #define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 371 #define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff 372 373 374 375 376 #define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c 377 #define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 378 #define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 379 #define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff 380 381 382 383 #endif 384