1*5113495bSYour Name 2*5113495bSYour Name /* 3*5113495bSYour Name * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * SPDX-License-Identifier: ISC 5*5113495bSYour Name */ 6*5113495bSYour Name 7*5113495bSYour Name 8*5113495bSYour Name 9*5113495bSYour Name 10*5113495bSYour Name 11*5113495bSYour Name 12*5113495bSYour Name 13*5113495bSYour Name 14*5113495bSYour Name 15*5113495bSYour Name 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name #ifndef _RX_REO_QUEUE_REFERENCE_H_ 20*5113495bSYour Name #define _RX_REO_QUEUE_REFERENCE_H_ 21*5113495bSYour Name #if !defined(__ASSEMBLER__) 22*5113495bSYour Name #endif 23*5113495bSYour Name 24*5113495bSYour Name #define NUM_OF_DWORDS_RX_REO_QUEUE_REFERENCE 2 25*5113495bSYour Name 26*5113495bSYour Name 27*5113495bSYour Name struct rx_reo_queue_reference { 28*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29*5113495bSYour Name uint32_t rx_reo_queue_desc_addr_31_0 : 32; 30*5113495bSYour Name uint32_t rx_reo_queue_desc_addr_39_32 : 8, 31*5113495bSYour Name reserved_1 : 8, 32*5113495bSYour Name receive_queue_number : 16; 33*5113495bSYour Name #else 34*5113495bSYour Name uint32_t rx_reo_queue_desc_addr_31_0 : 32; 35*5113495bSYour Name uint32_t receive_queue_number : 16, 36*5113495bSYour Name reserved_1 : 8, 37*5113495bSYour Name rx_reo_queue_desc_addr_39_32 : 8; 38*5113495bSYour Name #endif 39*5113495bSYour Name }; 40*5113495bSYour Name 41*5113495bSYour Name 42*5113495bSYour Name 43*5113495bSYour Name 44*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000000 45*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 46*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 47*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 48*5113495bSYour Name 49*5113495bSYour Name 50*5113495bSYour Name 51*5113495bSYour Name 52*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000004 53*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 54*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 55*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 56*5113495bSYour Name 57*5113495bSYour Name 58*5113495bSYour Name 59*5113495bSYour Name 60*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RESERVED_1_OFFSET 0x00000004 61*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RESERVED_1_LSB 8 62*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RESERVED_1_MSB 15 63*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RESERVED_1_MASK 0x0000ff00 64*5113495bSYour Name 65*5113495bSYour Name 66*5113495bSYour Name 67*5113495bSYour Name 68*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 69*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_LSB 16 70*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MSB 31 71*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 72*5113495bSYour Name 73*5113495bSYour Name 74*5113495bSYour Name 75*5113495bSYour Name #endif 76