1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_RESPONSE_REQUIRED_INFO_H_ 20 #define _RX_RESPONSE_REQUIRED_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "mlo_sta_id_details.h" 25 #define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 26 27 #define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 28 29 30 struct rx_response_required_info { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t phy_ppdu_id : 16, 33 su_or_uplink_mu_reception : 1, 34 trigger_frame_received : 1, 35 ftm_tm : 2, 36 tb_ranging_response_required : 2, 37 mac_security : 1, 38 filter_pass_monitor_ovrd : 1, 39 ast_search_incomplete : 1, 40 r2r_end_status_to_follow : 1, 41 reserved_0a : 2, 42 three_or_more_type_subtypes : 1, 43 wait_sifs_config_valid : 1, 44 wait_sifs : 2; 45 uint32_t general_frame_control : 16, 46 second_frame_control : 16; 47 uint32_t duration : 16, 48 pkt_type : 4, 49 dot11ax_su_extended : 1, 50 rate_mcs : 4, 51 sgi : 2, 52 stbc : 1, 53 ldpc : 1, 54 ampdu : 1, 55 vht_ack : 1, 56 rts_ta_grp_bit : 1; 57 uint32_t ctrl_frame_soliciting_resp : 1, 58 ast_fail_for_dot11ax_su_ext : 1, 59 service_dynamic : 1, 60 m_pkt : 1, 61 sta_partial_aid : 12, 62 group_id : 6, 63 ctrl_resp_pwr_mgmt : 1, 64 response_indication : 2, 65 ndp_indication : 1, 66 ndp_frame_type : 3, 67 second_frame_control_valid : 1, 68 reserved_3a : 2; 69 uint32_t ack_id : 16, 70 ack_id_ext : 10, 71 agc_cbw : 3, 72 service_cbw : 3; 73 uint32_t response_sta_count : 7, 74 reserved : 4, 75 ht_vht_sig_cbw : 3, 76 cts_cbw : 3, 77 response_ack_count : 7, 78 response_assoc_ack_count : 7, 79 txop_duration_all_ones : 1; 80 uint32_t response_ba32_count : 7, 81 response_ba64_count : 7, 82 response_ba128_count : 7, 83 response_ba256_count : 7, 84 multi_tid : 1, 85 sw_response_tlv_from_crypto : 1, 86 dot11ax_dl_ul_flag : 1, 87 reserved_6a : 1; 88 uint32_t sw_response_frame_length : 16, 89 response_ba512_count : 7, 90 response_ba1024_count : 7, 91 reserved_7a : 2; 92 uint32_t addr1_31_0 : 32; 93 uint32_t addr1_47_32 : 16, 94 addr2_15_0 : 16; 95 uint32_t addr2_47_16 : 32; 96 uint32_t dot11ax_received_format_indication : 1, 97 dot11ax_received_dl_ul_flag : 1, 98 dot11ax_received_bss_color_id : 6, 99 dot11ax_received_spatial_reuse : 4, 100 dot11ax_received_cp_size : 2, 101 dot11ax_received_ltf_size : 2, 102 dot11ax_received_coding : 1, 103 dot11ax_received_dcm : 1, 104 dot11ax_received_doppler_indication : 1, 105 dot11ax_received_ext_ru_size : 4, 106 ftm_fields_valid : 1, 107 ftm_pe_nss : 3, 108 ftm_pe_ltf_size : 2, 109 ftm_pe_content : 1, 110 ftm_chain_csd_en : 1, 111 ftm_pe_chain_csd_en : 1; 112 uint32_t dot11ax_response_rate_source : 8, 113 dot11ax_ext_response_rate_source : 8, 114 sw_peer_id : 16; 115 uint32_t dot11be_puncture_bitmap : 16, 116 dot11be_response : 1, 117 punctured_response : 1, 118 eht_duplicate_mode : 2, 119 force_extra_symbol : 1, 120 reserved_13a : 5, 121 u_sig_puncture_pattern_encoding : 6; 122 struct mlo_sta_id_details mlo_sta_id_details_rx; 123 uint16_t he_a_control_response_time : 12, 124 reserved_after_struct16 : 4; 125 uint32_t tlv64_padding : 32; 126 #else 127 uint32_t wait_sifs : 2, 128 wait_sifs_config_valid : 1, 129 three_or_more_type_subtypes : 1, 130 reserved_0a : 2, 131 r2r_end_status_to_follow : 1, 132 ast_search_incomplete : 1, 133 filter_pass_monitor_ovrd : 1, 134 mac_security : 1, 135 tb_ranging_response_required : 2, 136 ftm_tm : 2, 137 trigger_frame_received : 1, 138 su_or_uplink_mu_reception : 1, 139 phy_ppdu_id : 16; 140 uint32_t second_frame_control : 16, 141 general_frame_control : 16; 142 uint32_t rts_ta_grp_bit : 1, 143 vht_ack : 1, 144 ampdu : 1, 145 ldpc : 1, 146 stbc : 1, 147 sgi : 2, 148 rate_mcs : 4, 149 dot11ax_su_extended : 1, 150 pkt_type : 4, 151 duration : 16; 152 uint32_t reserved_3a : 2, 153 second_frame_control_valid : 1, 154 ndp_frame_type : 3, 155 ndp_indication : 1, 156 response_indication : 2, 157 ctrl_resp_pwr_mgmt : 1, 158 group_id : 6, 159 sta_partial_aid : 12, 160 m_pkt : 1, 161 service_dynamic : 1, 162 ast_fail_for_dot11ax_su_ext : 1, 163 ctrl_frame_soliciting_resp : 1; 164 uint32_t service_cbw : 3, 165 agc_cbw : 3, 166 ack_id_ext : 10, 167 ack_id : 16; 168 uint32_t txop_duration_all_ones : 1, 169 response_assoc_ack_count : 7, 170 response_ack_count : 7, 171 cts_cbw : 3, 172 ht_vht_sig_cbw : 3, 173 reserved : 4, 174 response_sta_count : 7; 175 uint32_t reserved_6a : 1, 176 dot11ax_dl_ul_flag : 1, 177 sw_response_tlv_from_crypto : 1, 178 multi_tid : 1, 179 response_ba256_count : 7, 180 response_ba128_count : 7, 181 response_ba64_count : 7, 182 response_ba32_count : 7; 183 uint32_t reserved_7a : 2, 184 response_ba1024_count : 7, 185 response_ba512_count : 7, 186 sw_response_frame_length : 16; 187 uint32_t addr1_31_0 : 32; 188 uint32_t addr2_15_0 : 16, 189 addr1_47_32 : 16; 190 uint32_t addr2_47_16 : 32; 191 uint32_t ftm_pe_chain_csd_en : 1, 192 ftm_chain_csd_en : 1, 193 ftm_pe_content : 1, 194 ftm_pe_ltf_size : 2, 195 ftm_pe_nss : 3, 196 ftm_fields_valid : 1, 197 dot11ax_received_ext_ru_size : 4, 198 dot11ax_received_doppler_indication : 1, 199 dot11ax_received_dcm : 1, 200 dot11ax_received_coding : 1, 201 dot11ax_received_ltf_size : 2, 202 dot11ax_received_cp_size : 2, 203 dot11ax_received_spatial_reuse : 4, 204 dot11ax_received_bss_color_id : 6, 205 dot11ax_received_dl_ul_flag : 1, 206 dot11ax_received_format_indication : 1; 207 uint32_t sw_peer_id : 16, 208 dot11ax_ext_response_rate_source : 8, 209 dot11ax_response_rate_source : 8; 210 uint32_t u_sig_puncture_pattern_encoding : 6, 211 reserved_13a : 5, 212 force_extra_symbol : 1, 213 eht_duplicate_mode : 2, 214 punctured_response : 1, 215 dot11be_response : 1, 216 dot11be_puncture_bitmap : 16; 217 uint32_t reserved_after_struct16 : 4, 218 he_a_control_response_time : 12; 219 struct mlo_sta_id_details mlo_sta_id_details_rx; 220 uint32_t tlv64_padding : 32; 221 #endif 222 }; 223 224 225 226 227 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 228 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 229 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 230 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff 231 232 233 234 235 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 236 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 237 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 238 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 239 240 241 242 243 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 244 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 245 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 246 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 247 248 249 250 251 #define RX_RESPONSE_REQUIRED_INFO_FTM_TM_OFFSET 0x0000000000000000 252 #define RX_RESPONSE_REQUIRED_INFO_FTM_TM_LSB 18 253 #define RX_RESPONSE_REQUIRED_INFO_FTM_TM_MSB 19 254 #define RX_RESPONSE_REQUIRED_INFO_FTM_TM_MASK 0x00000000000c0000 255 256 257 258 259 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000000 260 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20 261 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21 262 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000300000 263 264 265 266 267 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 268 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 269 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 270 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 271 272 273 274 275 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 276 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 277 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 278 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 279 280 281 282 283 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 284 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 285 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 286 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 287 288 289 290 291 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 292 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 293 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 294 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 295 296 297 298 299 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_OFFSET 0x0000000000000000 300 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_LSB 26 301 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MSB 27 302 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MASK 0x000000000c000000 303 304 305 306 307 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 308 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 309 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 310 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 311 312 313 314 315 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 316 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 317 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 318 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 319 320 321 322 323 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 324 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 325 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 326 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 327 328 329 330 331 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 332 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 333 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 334 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 335 336 337 338 339 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 340 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 341 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 342 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 343 344 345 346 347 #define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 348 #define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 349 #define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 350 #define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff 351 352 353 354 355 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 356 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 357 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 358 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 359 360 361 362 363 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 364 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 365 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 366 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 367 368 369 370 371 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 372 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 373 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24 374 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000001e00000 375 376 377 378 379 #define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 380 #define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25 381 #define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26 382 #define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x0000000006000000 383 384 385 386 387 #define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 388 #define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27 389 #define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27 390 #define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000008000000 391 392 393 394 395 #define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 396 #define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28 397 #define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28 398 #define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000010000000 399 400 401 402 403 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 404 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29 405 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29 406 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000020000000 407 408 409 410 411 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 412 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30 413 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30 414 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x0000000040000000 415 416 417 418 419 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 420 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 421 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 422 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 423 424 425 426 427 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 428 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 429 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 430 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 431 432 433 434 435 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 436 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 437 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 438 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 439 440 441 442 443 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 444 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 445 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 446 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 447 448 449 450 451 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 452 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 453 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 454 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 455 456 457 458 459 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 460 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 461 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 462 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 463 464 465 466 467 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 468 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 469 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 470 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 471 472 473 474 475 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 476 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 477 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 478 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 479 480 481 482 483 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 484 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 485 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 486 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 487 488 489 490 491 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 492 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 493 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 494 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 495 496 497 498 499 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 500 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 501 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 502 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 503 504 505 506 507 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 508 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 509 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 510 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 511 512 513 514 515 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000000000008 516 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 62 517 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 63 518 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0xc000000000000000 519 520 521 522 523 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x0000000000000010 524 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0 525 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15 526 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x000000000000ffff 527 528 529 530 531 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 532 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 533 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 534 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 535 536 537 538 539 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 540 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 541 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 542 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 543 544 545 546 547 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 548 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 549 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 550 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 551 552 553 554 555 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 556 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 557 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 558 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 559 560 561 562 563 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 564 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 39 565 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 566 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000078000000000 567 568 569 570 571 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 572 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 573 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 574 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 575 576 577 578 579 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 580 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 581 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 582 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 583 584 585 586 587 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 588 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 589 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 590 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 591 592 593 594 595 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 596 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 597 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 598 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 599 600 601 602 603 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 604 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 605 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 606 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 607 608 609 610 611 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 612 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 613 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 614 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f 615 616 617 618 619 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 620 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 621 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 622 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 623 624 625 626 627 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 628 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 629 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 630 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 631 632 633 634 635 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 636 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 637 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 638 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 639 640 641 642 643 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 644 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 645 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 646 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 647 648 649 650 651 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 652 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 653 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 654 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 655 656 657 658 659 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 660 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 661 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 662 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 663 664 665 666 667 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_OFFSET 0x0000000000000018 668 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_LSB 31 669 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MSB 31 670 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MASK 0x0000000080000000 671 672 673 674 675 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 676 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 677 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 678 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 679 680 681 682 683 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 684 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 685 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 686 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 687 688 689 690 691 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 692 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 693 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 694 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 695 696 697 698 699 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 700 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 701 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 702 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 703 704 705 706 707 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 708 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 709 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 710 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff 711 712 713 714 715 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 716 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 717 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 718 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 719 720 721 722 723 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 724 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 725 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 726 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 727 728 729 730 731 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 732 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 733 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 734 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff 735 736 737 738 739 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 740 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 741 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 742 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 743 744 745 746 747 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 748 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 749 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 750 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 751 752 753 754 755 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 756 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 757 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 758 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 759 760 761 762 763 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 764 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 765 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 766 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 767 768 769 770 771 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 772 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 773 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 774 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 775 776 777 778 779 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 780 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 781 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 782 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 783 784 785 786 787 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 788 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 789 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 790 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 791 792 793 794 795 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 796 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 797 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 798 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 799 800 801 802 803 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 804 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 805 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 806 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 807 808 809 810 811 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 812 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 813 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 814 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 815 816 817 818 819 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 820 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 821 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 822 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 823 824 825 826 827 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 828 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 829 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 830 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 831 832 833 834 835 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 836 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 837 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 838 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 839 840 841 842 843 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 844 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 845 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 846 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 847 848 849 850 851 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 852 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 853 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 854 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 855 856 857 858 859 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 860 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 861 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 862 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 863 864 865 866 867 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 868 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 869 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 870 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff 871 872 873 874 875 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 876 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 877 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 878 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 879 880 881 882 883 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 884 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 885 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 886 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 887 888 889 890 891 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 892 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 893 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 894 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 895 896 897 898 899 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 900 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 901 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 902 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 903 904 905 906 907 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 908 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 909 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 910 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 911 912 913 914 915 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 916 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 917 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 918 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 919 920 921 922 923 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 924 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 925 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 926 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 927 928 929 930 931 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 932 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 53 933 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 934 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e0000000000000 935 936 937 938 939 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 940 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 941 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 942 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 943 944 945 946 947 948 949 950 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 951 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 952 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 953 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff 954 955 956 957 958 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 959 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 960 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 961 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 962 963 964 965 966 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 967 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 968 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 969 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 970 971 972 973 974 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 975 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 976 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 977 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 978 979 980 981 982 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 983 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 984 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 985 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 986 987 988 989 990 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 991 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 992 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 993 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 994 995 996 997 998 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 999 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 1000 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 1001 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 1002 1003 1004 1005 1006 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 1007 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_LSB 32 1008 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MSB 63 1009 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MASK 0xffffffff00000000 1010 1011 1012 1013 #endif 1014