xref: /wlan-driver/fw-api/hw/qca5424/rx_timing_offset_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc) 
1*5113495bSYour Name 
2*5113495bSYour Name /*
3*5113495bSYour Name  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name  * SPDX-License-Identifier: ISC
5*5113495bSYour Name  */
6*5113495bSYour Name 
7*5113495bSYour Name 
8*5113495bSYour Name 
9*5113495bSYour Name 
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12*5113495bSYour Name 
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17*5113495bSYour Name 
18*5113495bSYour Name 
19*5113495bSYour Name #ifndef _RX_TIMING_OFFSET_INFO_H_
20*5113495bSYour Name #define _RX_TIMING_OFFSET_INFO_H_
21*5113495bSYour Name #if !defined(__ASSEMBLER__)
22*5113495bSYour Name #endif
23*5113495bSYour Name 
24*5113495bSYour Name #define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1
25*5113495bSYour Name 
26*5113495bSYour Name 
27*5113495bSYour Name struct rx_timing_offset_info {
28*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
29*5113495bSYour Name              uint32_t residual_phase_offset                                   : 12,
30*5113495bSYour Name                       reserved                                                : 20;
31*5113495bSYour Name #else
32*5113495bSYour Name              uint32_t reserved                                                : 20,
33*5113495bSYour Name                       residual_phase_offset                                   : 12;
34*5113495bSYour Name #endif
35*5113495bSYour Name };
36*5113495bSYour Name 
37*5113495bSYour Name 
38*5113495bSYour Name 
39*5113495bSYour Name 
40*5113495bSYour Name #define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_OFFSET                          0x00000000
41*5113495bSYour Name #define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_LSB                             0
42*5113495bSYour Name #define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MSB                             11
43*5113495bSYour Name #define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MASK                            0x00000fff
44*5113495bSYour Name 
45*5113495bSYour Name 
46*5113495bSYour Name 
47*5113495bSYour Name 
48*5113495bSYour Name #define RX_TIMING_OFFSET_INFO_RESERVED_OFFSET                                       0x00000000
49*5113495bSYour Name #define RX_TIMING_OFFSET_INFO_RESERVED_LSB                                          12
50*5113495bSYour Name #define RX_TIMING_OFFSET_INFO_RESERVED_MSB                                          31
51*5113495bSYour Name #define RX_TIMING_OFFSET_INFO_RESERVED_MASK                                         0xfffff000
52*5113495bSYour Name 
53*5113495bSYour Name 
54*5113495bSYour Name 
55*5113495bSYour Name #endif
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