1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RXPCU_EARLY_RX_INDICATION_H_ 20 #define _RXPCU_EARLY_RX_INDICATION_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 25 26 #define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 27 28 29 struct rxpcu_early_rx_indication { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t pkt_type : 4, 32 dot11ax_su_extended : 1, 33 rate_mcs : 4, 34 dot11ax_received_ext_ru_size : 4, 35 reserved_0a : 19; 36 uint32_t tlv64_padding : 32; 37 #else 38 uint32_t reserved_0a : 19, 39 dot11ax_received_ext_ru_size : 4, 40 rate_mcs : 4, 41 dot11ax_su_extended : 1, 42 pkt_type : 4; 43 uint32_t tlv64_padding : 32; 44 #endif 45 }; 46 47 48 49 50 #define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 51 #define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 52 #define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 53 #define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f 54 55 56 57 58 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 59 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 60 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 61 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 62 63 64 65 66 #define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 67 #define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 68 #define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 8 69 #define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000001e0 70 71 72 73 74 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 75 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 9 76 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 12 77 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000001e00 78 79 80 81 82 #define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 83 #define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 13 84 #define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 85 #define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffe000 86 87 88 89 90 #define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 91 #define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 92 #define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 93 #define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 94 95 96 97 #endif 98