1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RXPCU_PPDU_END_INFO_H_ 20 #define _RXPCU_PPDU_END_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "phyrx_abort_request_info.h" 25 #include "macrx_abort_request_info.h" 26 #include "rxpcu_ppdu_end_layout_info.h" 27 #define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 28 28 29 #define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 14 30 31 32 struct rxpcu_ppdu_end_info { 33 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34 uint32_t wb_timestamp_lower_32 : 32; 35 uint32_t wb_timestamp_upper_32 : 32; 36 uint32_t rx_antenna : 24, 37 tx_ht_vht_ack : 1, 38 unsupported_mu_nc : 1, 39 otp_txbf_disable : 1, 40 previous_tlv_corrupted : 1, 41 phyrx_abort_request_info_valid : 1, 42 macrx_abort_request_info_valid : 1, 43 reserved : 2; 44 uint32_t coex_bt_tx_from_start_of_rx : 1, 45 coex_bt_tx_after_start_of_rx : 1, 46 coex_wan_tx_from_start_of_rx : 1, 47 coex_wan_tx_after_start_of_rx : 1, 48 coex_wlan_tx_from_start_of_rx : 1, 49 coex_wlan_tx_after_start_of_rx : 1, 50 mpdu_delimiter_errors_seen : 1, 51 ftm_tm : 2, 52 dialog_token : 8, 53 follow_up_dialog_token : 8, 54 bb_captured_channel : 1, 55 bb_captured_reason : 3, 56 bb_captured_timeout : 1, 57 reserved_3 : 2; 58 uint32_t before_mpdu_count_passing_fcs : 10, 59 before_mpdu_count_failing_fcs : 10, 60 after_mpdu_count_passing_fcs : 10, 61 reserved_4 : 2; 62 uint32_t after_mpdu_count_failing_fcs : 10, 63 reserved_5 : 22; 64 uint32_t phy_timestamp_tx_lower_32 : 32; 65 uint32_t phy_timestamp_tx_upper_32 : 32; 66 uint32_t bb_length : 16, 67 bb_data : 1, 68 reserved_8 : 3, 69 first_bt_broadcast_status_details : 12; 70 uint32_t rx_ppdu_duration : 24, 71 reserved_9 : 8; 72 uint32_t ast_index : 16, 73 ast_index_valid : 1, 74 reserved_10 : 3, 75 second_bt_broadcast_status_details : 12; 76 struct phyrx_abort_request_info phyrx_abort_request_info_details; 77 struct macrx_abort_request_info macrx_abort_request_info_details; 78 uint16_t pre_bt_broadcast_status_details : 12, 79 reserved_12a : 4; 80 uint32_t non_qos_sn_info_valid : 1, 81 reserved_13a : 5, 82 non_qos_sn_highest : 12, 83 non_qos_sn_highest_retry_setting : 1, 84 non_qos_sn_lowest : 12, 85 non_qos_sn_lowest_retry_setting : 1; 86 uint32_t qos_sn_1_info_valid : 1, 87 reserved_14a : 1, 88 qos_sn_1_tid : 4, 89 qos_sn_1_highest : 12, 90 qos_sn_1_highest_retry_setting : 1, 91 qos_sn_1_lowest : 12, 92 qos_sn_1_lowest_retry_setting : 1; 93 uint32_t qos_sn_2_info_valid : 1, 94 reserved_15a : 1, 95 qos_sn_2_tid : 4, 96 qos_sn_2_highest : 12, 97 qos_sn_2_highest_retry_setting : 1, 98 qos_sn_2_lowest : 12, 99 qos_sn_2_lowest_retry_setting : 1; 100 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 101 uint32_t corrupted_due_to_fifo_delay : 1, 102 qos_sn_1_more_frag_state : 1, 103 qos_sn_1_frag_num_state : 4, 104 qos_sn_2_more_frag_state : 1, 105 qos_sn_2_frag_num_state : 4, 106 reserved_26a : 21; 107 uint32_t rx_ppdu_end_marker : 32; 108 #else 109 uint32_t wb_timestamp_lower_32 : 32; 110 uint32_t wb_timestamp_upper_32 : 32; 111 uint32_t reserved : 2, 112 macrx_abort_request_info_valid : 1, 113 phyrx_abort_request_info_valid : 1, 114 previous_tlv_corrupted : 1, 115 otp_txbf_disable : 1, 116 unsupported_mu_nc : 1, 117 tx_ht_vht_ack : 1, 118 rx_antenna : 24; 119 uint32_t reserved_3 : 2, 120 bb_captured_timeout : 1, 121 bb_captured_reason : 3, 122 bb_captured_channel : 1, 123 follow_up_dialog_token : 8, 124 dialog_token : 8, 125 ftm_tm : 2, 126 mpdu_delimiter_errors_seen : 1, 127 coex_wlan_tx_after_start_of_rx : 1, 128 coex_wlan_tx_from_start_of_rx : 1, 129 coex_wan_tx_after_start_of_rx : 1, 130 coex_wan_tx_from_start_of_rx : 1, 131 coex_bt_tx_after_start_of_rx : 1, 132 coex_bt_tx_from_start_of_rx : 1; 133 uint32_t reserved_4 : 2, 134 after_mpdu_count_passing_fcs : 10, 135 before_mpdu_count_failing_fcs : 10, 136 before_mpdu_count_passing_fcs : 10; 137 uint32_t reserved_5 : 22, 138 after_mpdu_count_failing_fcs : 10; 139 uint32_t phy_timestamp_tx_lower_32 : 32; 140 uint32_t phy_timestamp_tx_upper_32 : 32; 141 uint32_t first_bt_broadcast_status_details : 12, 142 reserved_8 : 3, 143 bb_data : 1, 144 bb_length : 16; 145 uint32_t reserved_9 : 8, 146 rx_ppdu_duration : 24; 147 uint32_t second_bt_broadcast_status_details : 12, 148 reserved_10 : 3, 149 ast_index_valid : 1, 150 ast_index : 16; 151 struct phyrx_abort_request_info phyrx_abort_request_info_details; 152 uint32_t reserved_12a : 4, 153 pre_bt_broadcast_status_details : 12; 154 struct macrx_abort_request_info macrx_abort_request_info_details; 155 uint32_t non_qos_sn_lowest_retry_setting : 1, 156 non_qos_sn_lowest : 12, 157 non_qos_sn_highest_retry_setting : 1, 158 non_qos_sn_highest : 12, 159 reserved_13a : 5, 160 non_qos_sn_info_valid : 1; 161 uint32_t qos_sn_1_lowest_retry_setting : 1, 162 qos_sn_1_lowest : 12, 163 qos_sn_1_highest_retry_setting : 1, 164 qos_sn_1_highest : 12, 165 qos_sn_1_tid : 4, 166 reserved_14a : 1, 167 qos_sn_1_info_valid : 1; 168 uint32_t qos_sn_2_lowest_retry_setting : 1, 169 qos_sn_2_lowest : 12, 170 qos_sn_2_highest_retry_setting : 1, 171 qos_sn_2_highest : 12, 172 qos_sn_2_tid : 4, 173 reserved_15a : 1, 174 qos_sn_2_info_valid : 1; 175 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 176 uint32_t reserved_26a : 21, 177 qos_sn_2_frag_num_state : 4, 178 qos_sn_2_more_frag_state : 1, 179 qos_sn_1_frag_num_state : 4, 180 qos_sn_1_more_frag_state : 1, 181 corrupted_due_to_fifo_delay : 1; 182 uint32_t rx_ppdu_end_marker : 32; 183 #endif 184 }; 185 186 187 188 189 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 190 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 191 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 192 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff 193 194 195 196 197 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 198 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 199 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 200 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 201 202 203 204 205 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 206 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 207 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 208 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff 209 210 211 212 213 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 214 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 215 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 216 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 217 218 219 220 221 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 222 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 223 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 224 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 225 226 227 228 229 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 230 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 231 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 232 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 233 234 235 236 237 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 238 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 239 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 240 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 241 242 243 244 245 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 246 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 247 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 248 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 249 250 251 252 253 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 254 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 255 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 256 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 257 258 259 260 261 #define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x0000000000000008 262 #define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 263 #define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 264 #define RXPCU_PPDU_END_INFO_RESERVED_MASK 0x00000000c0000000 265 266 267 268 269 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 270 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 271 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 272 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 273 274 275 276 277 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 278 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 279 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 280 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 281 282 283 284 285 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 286 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 287 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 288 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 289 290 291 292 293 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 294 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 295 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 296 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 297 298 299 300 301 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 302 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 303 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 304 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 305 306 307 308 309 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 310 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 311 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 312 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 313 314 315 316 317 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 318 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 319 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 320 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 321 322 323 324 325 #define RXPCU_PPDU_END_INFO_FTM_TM_OFFSET 0x0000000000000008 326 #define RXPCU_PPDU_END_INFO_FTM_TM_LSB 39 327 #define RXPCU_PPDU_END_INFO_FTM_TM_MSB 40 328 #define RXPCU_PPDU_END_INFO_FTM_TM_MASK 0x0000018000000000 329 330 331 332 333 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 334 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 335 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 336 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 337 338 339 340 341 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 342 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 343 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 344 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 345 346 347 348 349 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 350 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 351 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 352 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 353 354 355 356 357 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 358 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 359 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 360 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 361 362 363 364 365 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 366 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 367 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 368 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 369 370 371 372 373 #define RXPCU_PPDU_END_INFO_RESERVED_3_OFFSET 0x0000000000000008 374 #define RXPCU_PPDU_END_INFO_RESERVED_3_LSB 62 375 #define RXPCU_PPDU_END_INFO_RESERVED_3_MSB 63 376 #define RXPCU_PPDU_END_INFO_RESERVED_3_MASK 0xc000000000000000 377 378 379 380 381 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 382 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 383 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 384 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff 385 386 387 388 389 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 390 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 391 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 392 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 393 394 395 396 397 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 398 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 399 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 400 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 401 402 403 404 405 #define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 406 #define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 407 #define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 408 #define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 409 410 411 412 413 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 414 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 415 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 416 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 417 418 419 420 421 #define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 422 #define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 423 #define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 424 #define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 425 426 427 428 429 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 430 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 431 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 432 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff 433 434 435 436 437 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 438 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 439 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 440 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 441 442 443 444 445 #define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 446 #define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 447 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 448 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff 449 450 451 452 453 #define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 454 #define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 455 #define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 456 #define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 457 458 459 460 461 #define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 462 #define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 463 #define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 464 #define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 465 466 467 468 469 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 470 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 471 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 472 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 473 474 475 476 477 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 478 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 479 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 480 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 481 482 483 484 485 #define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 486 #define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 487 #define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 488 #define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 489 490 491 492 493 #define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 494 #define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 495 #define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 496 #define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff 497 498 499 500 501 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 502 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 503 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 504 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 505 506 507 508 509 #define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 510 #define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 511 #define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 512 #define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 513 514 515 516 517 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 518 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 519 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 520 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 521 522 523 524 525 526 527 528 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 529 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 530 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 531 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 532 533 534 535 536 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 537 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 538 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 539 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 540 541 542 543 544 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 545 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 546 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 547 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 548 549 550 551 552 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 553 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 42 554 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 555 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc0000000000 556 557 558 559 560 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 561 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 562 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 563 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 564 565 566 567 568 569 570 571 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 572 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 573 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 574 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff 575 576 577 578 579 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 580 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 581 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 582 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 583 584 585 586 587 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 588 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 589 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 590 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 591 592 593 594 595 #define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 596 #define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 597 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 598 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 599 600 601 602 603 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 604 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 605 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 606 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 607 608 609 610 611 #define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 612 #define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 33 613 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 614 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003e00000000 615 616 617 618 619 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 620 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 621 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 622 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 623 624 625 626 627 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 628 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 629 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 630 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 631 632 633 634 635 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 636 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 637 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 638 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 639 640 641 642 643 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 644 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 645 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 646 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 647 648 649 650 651 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 652 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 653 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 654 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 655 656 657 658 659 #define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 660 #define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 661 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 662 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 663 664 665 666 667 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 668 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 669 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 670 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c 671 672 673 674 675 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 676 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 677 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 678 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 679 680 681 682 683 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 684 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 685 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 686 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 687 688 689 690 691 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 692 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 693 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 694 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 695 696 697 698 699 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 700 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 701 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 702 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 703 704 705 706 707 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 708 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 709 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 710 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 711 712 713 714 715 #define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 716 #define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 717 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 718 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 719 720 721 722 723 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 724 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 725 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 726 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 727 728 729 730 731 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 732 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 733 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 734 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 735 736 737 738 739 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 740 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 741 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 742 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 743 744 745 746 747 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 748 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 749 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 750 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 751 752 753 754 755 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 756 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 757 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 758 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 759 760 761 762 763 764 765 766 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 767 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 768 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 769 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 770 771 772 773 774 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 775 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 776 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 777 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc 778 779 780 781 782 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 783 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 784 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 785 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 786 787 788 789 790 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 791 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 792 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 793 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 794 795 796 797 798 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 799 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 800 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 801 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 802 803 804 805 806 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 807 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 808 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 809 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 810 811 812 813 814 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 815 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 816 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 817 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 818 819 820 821 822 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 823 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 824 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 825 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 826 827 828 829 830 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 831 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 832 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 833 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 834 835 836 837 838 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 839 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 840 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 841 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 842 843 844 845 846 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 847 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 848 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 849 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 850 851 852 853 854 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 855 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 856 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 857 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 858 859 860 861 862 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 863 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 864 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 865 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f 866 867 868 869 870 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 871 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 872 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 873 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 874 875 876 877 878 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 879 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 880 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 881 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 882 883 884 885 886 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 887 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 888 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 889 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 890 891 892 893 894 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 895 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 896 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 897 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 898 899 900 901 902 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 903 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 904 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 905 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 906 907 908 909 910 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 911 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 912 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 913 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 914 915 916 917 918 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 919 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 920 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 921 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 922 923 924 925 926 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 927 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 928 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 929 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 930 931 932 933 934 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 935 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 936 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 937 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 938 939 940 941 942 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 943 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 944 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 945 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f 946 947 948 949 950 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 951 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 952 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 953 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 954 955 956 957 958 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 959 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 960 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 961 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 962 963 964 965 966 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 967 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 968 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 969 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 970 971 972 973 974 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 975 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 976 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 977 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 978 979 980 981 982 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 983 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 984 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 985 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 986 987 988 989 990 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 991 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 992 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 993 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 994 995 996 997 998 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 999 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 1000 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 1001 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 1002 1003 1004 1005 1006 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 1007 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 1008 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 1009 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 1010 1011 1012 1013 1014 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 1015 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 1016 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 1017 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 1018 1019 1020 1021 1022 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 1023 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 1024 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 1025 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 1026 1027 1028 1029 1030 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 1031 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 1032 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 1033 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 1034 1035 1036 1037 1038 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 1039 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 1040 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 1041 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff 1042 1043 1044 1045 1046 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 1047 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 1048 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 1049 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 1050 1051 1052 1053 1054 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 1055 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 1056 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 1057 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 1058 1059 1060 1061 1062 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 1063 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 1064 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 1065 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 1066 1067 1068 1069 1070 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000000000000058 1071 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_LSB 32 1072 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MSB 39 1073 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff00000000 1074 1075 1076 1077 1078 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 1079 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 1080 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 1081 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 1082 1083 1084 1085 1086 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 1087 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 1088 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 1089 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 1090 1091 1092 1093 1094 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 1095 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 1096 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 1097 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 1098 1099 1100 1101 1102 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 1103 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 1104 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 1105 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff 1106 1107 1108 1109 1110 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 1111 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 1112 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 1113 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 1114 1115 1116 1117 1118 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 1119 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 1120 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 1121 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 1122 1123 1124 1125 1126 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 1127 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 1128 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 1129 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 1130 1131 1132 1133 1134 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 1135 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 1136 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 1137 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c 1138 1139 1140 1141 1142 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 1143 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 1144 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 1145 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 1146 1147 1148 1149 1150 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 1151 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 1152 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 1153 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 1154 1155 1156 1157 1158 #define RXPCU_PPDU_END_INFO_RESERVED_26A_OFFSET 0x0000000000000068 1159 #define RXPCU_PPDU_END_INFO_RESERVED_26A_LSB 11 1160 #define RXPCU_PPDU_END_INFO_RESERVED_26A_MSB 31 1161 #define RXPCU_PPDU_END_INFO_RESERVED_26A_MASK 0x00000000fffff800 1162 1163 1164 1165 1166 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000068 1167 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 1168 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 1169 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 1170 1171 1172 1173 #endif 1174