1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TCL_GSE_CMD_H_ 20 #define _TCL_GSE_CMD_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TCL_GSE_CMD 8 25 26 27 struct tcl_gse_cmd { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t control_buffer_addr_31_0 : 32; 30 uint32_t control_buffer_addr_39_32 : 8, 31 gse_ctrl : 4, 32 gse_sel : 1, 33 status_destination_ring_id : 1, 34 swap : 1, 35 index_search_en : 1, 36 cache_set_num : 4, 37 reserved_1a : 12; 38 uint32_t tcl_cmd_type : 1, 39 reserved_2a : 31; 40 uint32_t cmd_meta_data_31_0 : 32; 41 uint32_t cmd_meta_data_63_32 : 32; 42 uint32_t reserved_5a : 32; 43 uint32_t reserved_6a : 32; 44 uint32_t reserved_7a : 20, 45 ring_id : 8, 46 looping_count : 4; 47 #else 48 uint32_t control_buffer_addr_31_0 : 32; 49 uint32_t reserved_1a : 12, 50 cache_set_num : 4, 51 index_search_en : 1, 52 swap : 1, 53 status_destination_ring_id : 1, 54 gse_sel : 1, 55 gse_ctrl : 4, 56 control_buffer_addr_39_32 : 8; 57 uint32_t reserved_2a : 31, 58 tcl_cmd_type : 1; 59 uint32_t cmd_meta_data_31_0 : 32; 60 uint32_t cmd_meta_data_63_32 : 32; 61 uint32_t reserved_5a : 32; 62 uint32_t reserved_6a : 32; 63 uint32_t looping_count : 4, 64 ring_id : 8, 65 reserved_7a : 20; 66 #endif 67 }; 68 69 70 71 72 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 73 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 74 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 75 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 76 77 78 79 80 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 81 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 82 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 83 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 84 85 86 87 88 #define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 89 #define TCL_GSE_CMD_GSE_CTRL_LSB 8 90 #define TCL_GSE_CMD_GSE_CTRL_MSB 11 91 #define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 92 93 94 95 96 #define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 97 #define TCL_GSE_CMD_GSE_SEL_LSB 12 98 #define TCL_GSE_CMD_GSE_SEL_MSB 12 99 #define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 100 101 102 103 104 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 105 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 106 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 107 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 108 109 110 111 112 #define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 113 #define TCL_GSE_CMD_SWAP_LSB 14 114 #define TCL_GSE_CMD_SWAP_MSB 14 115 #define TCL_GSE_CMD_SWAP_MASK 0x00004000 116 117 118 119 120 #define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 121 #define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 122 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 123 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 124 125 126 127 128 #define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 129 #define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 130 #define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 131 #define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 132 133 134 135 136 #define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 137 #define TCL_GSE_CMD_RESERVED_1A_LSB 20 138 #define TCL_GSE_CMD_RESERVED_1A_MSB 31 139 #define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 140 141 142 143 144 #define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 145 #define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 146 #define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 147 #define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 148 149 150 151 152 #define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 153 #define TCL_GSE_CMD_RESERVED_2A_LSB 1 154 #define TCL_GSE_CMD_RESERVED_2A_MSB 31 155 #define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe 156 157 158 159 160 #define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c 161 #define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 162 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 163 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff 164 165 166 167 168 #define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 169 #define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 170 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 171 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff 172 173 174 175 176 #define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 177 #define TCL_GSE_CMD_RESERVED_5A_LSB 0 178 #define TCL_GSE_CMD_RESERVED_5A_MSB 31 179 #define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff 180 181 182 183 184 #define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 185 #define TCL_GSE_CMD_RESERVED_6A_LSB 0 186 #define TCL_GSE_CMD_RESERVED_6A_MSB 31 187 #define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff 188 189 190 191 192 #define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c 193 #define TCL_GSE_CMD_RESERVED_7A_LSB 0 194 #define TCL_GSE_CMD_RESERVED_7A_MSB 19 195 #define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff 196 197 198 199 200 #define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c 201 #define TCL_GSE_CMD_RING_ID_LSB 20 202 #define TCL_GSE_CMD_RING_ID_MSB 27 203 #define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 204 205 206 207 208 #define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c 209 #define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 210 #define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 211 #define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 212 213 214 215 #endif 216