1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TCL_STATUS_RING_H_ 20 #define _TCL_STATUS_RING_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TCL_STATUS_RING 8 25 26 27 struct tcl_status_ring { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t gse_ctrl : 4, 30 ase_fse_sel : 1, 31 cache_op_res : 2, 32 index_search_en : 1, 33 msdu_cnt_n : 24; 34 uint32_t msdu_byte_cnt_n : 32; 35 uint32_t msdu_timestmp_n : 32; 36 uint32_t cmd_meta_data_31_0 : 32; 37 uint32_t cmd_meta_data_63_32 : 32; 38 uint32_t hash_indx_val : 20, 39 cache_set_num : 4, 40 reserved_5a : 8; 41 uint32_t reserved_6a : 32; 42 uint32_t reserved_7a : 20, 43 ring_id : 8, 44 looping_count : 4; 45 #else 46 uint32_t msdu_cnt_n : 24, 47 index_search_en : 1, 48 cache_op_res : 2, 49 ase_fse_sel : 1, 50 gse_ctrl : 4; 51 uint32_t msdu_byte_cnt_n : 32; 52 uint32_t msdu_timestmp_n : 32; 53 uint32_t cmd_meta_data_31_0 : 32; 54 uint32_t cmd_meta_data_63_32 : 32; 55 uint32_t reserved_5a : 8, 56 cache_set_num : 4, 57 hash_indx_val : 20; 58 uint32_t reserved_6a : 32; 59 uint32_t looping_count : 4, 60 ring_id : 8, 61 reserved_7a : 20; 62 #endif 63 }; 64 65 66 67 68 #define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 69 #define TCL_STATUS_RING_GSE_CTRL_LSB 0 70 #define TCL_STATUS_RING_GSE_CTRL_MSB 3 71 #define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f 72 73 74 75 76 #define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 77 #define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 78 #define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 79 #define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 80 81 82 83 84 #define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 85 #define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 86 #define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 87 #define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 88 89 90 91 92 #define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 93 #define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 94 #define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 95 #define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 96 97 98 99 100 #define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 101 #define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 102 #define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 103 #define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 104 105 106 107 108 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 109 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 110 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 111 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff 112 113 114 115 116 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 117 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 118 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 119 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff 120 121 122 123 124 #define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c 125 #define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 126 #define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 127 #define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff 128 129 130 131 132 #define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 133 #define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 134 #define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 135 #define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff 136 137 138 139 140 #define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 141 #define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 142 #define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 143 #define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff 144 145 146 147 148 #define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 149 #define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 150 #define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 151 #define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 152 153 154 155 156 #define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 157 #define TCL_STATUS_RING_RESERVED_5A_LSB 24 158 #define TCL_STATUS_RING_RESERVED_5A_MSB 31 159 #define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 160 161 162 163 164 #define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 165 #define TCL_STATUS_RING_RESERVED_6A_LSB 0 166 #define TCL_STATUS_RING_RESERVED_6A_MSB 31 167 #define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff 168 169 170 171 172 #define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c 173 #define TCL_STATUS_RING_RESERVED_7A_LSB 0 174 #define TCL_STATUS_RING_RESERVED_7A_MSB 19 175 #define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff 176 177 178 179 180 #define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c 181 #define TCL_STATUS_RING_RING_ID_LSB 20 182 #define TCL_STATUS_RING_RING_ID_MSB 27 183 #define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 184 185 186 187 188 #define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c 189 #define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 190 #define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 191 #define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 192 193 194 195 #endif 196