1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TX_FES_STATUS_END_H_ 20 #define _TX_FES_STATUS_END_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "phytx_abort_request_info.h" 25 #define NUM_OF_DWORDS_TX_FES_STATUS_END 22 26 27 #define NUM_OF_QWORDS_TX_FES_STATUS_END 11 28 29 30 struct tx_fes_status_end { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t prot_coex_bt_tx_while_wlan_tx : 1, 33 prot_coex_bt_tx_while_wlan_rx : 1, 34 prot_coex_wan_tx_while_wlan_tx : 1, 35 prot_coex_wan_tx_while_wlan_rx : 1, 36 prot_coex_wlan_tx_while_wlan_tx : 1, 37 prot_coex_wlan_tx_while_wlan_rx : 1, 38 coex_bt_tx_while_wlan_tx : 1, 39 coex_bt_tx_while_wlan_rx : 1, 40 coex_wan_tx_while_wlan_tx : 1, 41 coex_wan_tx_while_wlan_rx : 1, 42 coex_wlan_tx_while_wlan_tx : 1, 43 coex_wlan_tx_while_wlan_rx : 1, 44 global_data_underflow_warning : 1, 45 global_fes_transmit_result : 4, 46 cbf_bw_received_valid : 1, 47 cbf_bw_received : 3, 48 actual_received_ack_type : 4, 49 sta_response_count : 6, 50 dpdtrain_done : 1; 51 struct phytx_abort_request_info phytx_abort_request_info_details; 52 uint16_t reserved_after_struct16 : 4, 53 brp_info_valid : 1, 54 reserved_1a : 6, 55 phytx_pkt_end_info_valid : 1, 56 phytx_abort_request_info_valid : 1, 57 fes_in_11ax_trigger_response_config : 1, 58 null_delim_inserted_before_mpdus : 1, 59 only_null_delim_sent : 1; 60 uint32_t start_of_frame_timestamp_15_0 : 16, 61 start_of_frame_timestamp_31_16 : 16; 62 uint32_t end_of_frame_timestamp_15_0 : 16, 63 end_of_frame_timestamp_31_16 : 16; 64 uint32_t terminate_ranging_sequence : 1, 65 reserved_4a : 7, 66 timing_status : 2, 67 response_type : 5, 68 r2r_end_status_to_follow : 1, 69 transmit_delay : 16; 70 uint32_t tx_group_delay : 12, 71 reserved_5a : 4, 72 tpc_dbg_info_cmn_15_0 : 16; 73 uint32_t tpc_dbg_info_cmn_31_16 : 16, 74 tpc_dbg_info_47_32 : 16; 75 uint32_t tpc_dbg_info_chn1_15_0 : 16, 76 tpc_dbg_info_chn1_31_16 : 16; 77 uint32_t tpc_dbg_info_chn1_47_32 : 16, 78 tpc_dbg_info_chn1_63_48 : 16; 79 uint32_t tpc_dbg_info_chn1_79_64 : 16, 80 tpc_dbg_info_chn2_15_0 : 16; 81 uint32_t tpc_dbg_info_chn2_31_16 : 16, 82 tpc_dbg_info_chn2_47_32 : 16; 83 uint32_t tpc_dbg_info_chn2_63_48 : 16, 84 tpc_dbg_info_chn2_79_64 : 16; 85 uint32_t phytx_tx_end_sw_info_15_0 : 16, 86 phytx_tx_end_sw_info_31_16 : 16; 87 uint32_t phytx_tx_end_sw_info_47_32 : 16, 88 phytx_tx_end_sw_info_63_48 : 16; 89 uint32_t beamform_masked_user_bitmap_15_0 : 16, 90 beamform_masked_user_bitmap_31_16 : 16; 91 uint32_t cbf_segment_request_mask : 8, 92 cbf_segment_sent_mask : 8, 93 highest_achieved_data_null_ratio : 5, 94 use_alt_power_sr : 1, 95 static_2_pwr_mode_status : 1, 96 obss_srg_opport_transmit_status : 1, 97 srp_based_transmit_status : 1, 98 obss_pd_based_transmit_status : 1, 99 beamform_masked_user_bitmap_36_32 : 5, 100 pdg_mpdu_ready : 1; 101 uint32_t pdg_mpdu_count : 16, 102 pdg_est_mpdu_tx_count : 16; 103 uint32_t pdg_overview_length : 24, 104 txop_duration : 7, 105 pdg_dropped_mpdu_warning : 1; 106 uint32_t packet_extension_a_factor : 2, 107 packet_extension_pe_disambiguity : 1, 108 packet_extension : 3, 109 fec_type : 1, 110 stbc : 1, 111 num_data_symbols : 16, 112 ru_size : 4, 113 reserved_17a : 4; 114 uint32_t num_ltf_symbols : 3, 115 ltf_size : 2, 116 cp_setting : 2, 117 reserved_18a : 5, 118 dcm : 1, 119 ldpc_extra_symbol : 1, 120 force_extra_symbol : 1, 121 reserved_18b : 1, 122 tx_pwr_shared : 8, 123 tx_pwr_unshared : 8; 124 uint32_t ranging_active_user_map : 16, 125 ranging_sent_dummy_tx : 1, 126 ranging_ftm_frame_sent : 1, 127 reserved_20a : 6, 128 cv_corr_status : 8; 129 uint32_t current_tx_duration : 16, 130 reserved_21a : 16; 131 #else 132 uint32_t dpdtrain_done : 1, 133 sta_response_count : 6, 134 actual_received_ack_type : 4, 135 cbf_bw_received : 3, 136 cbf_bw_received_valid : 1, 137 global_fes_transmit_result : 4, 138 global_data_underflow_warning : 1, 139 coex_wlan_tx_while_wlan_rx : 1, 140 coex_wlan_tx_while_wlan_tx : 1, 141 coex_wan_tx_while_wlan_rx : 1, 142 coex_wan_tx_while_wlan_tx : 1, 143 coex_bt_tx_while_wlan_rx : 1, 144 coex_bt_tx_while_wlan_tx : 1, 145 prot_coex_wlan_tx_while_wlan_rx : 1, 146 prot_coex_wlan_tx_while_wlan_tx : 1, 147 prot_coex_wan_tx_while_wlan_rx : 1, 148 prot_coex_wan_tx_while_wlan_tx : 1, 149 prot_coex_bt_tx_while_wlan_rx : 1, 150 prot_coex_bt_tx_while_wlan_tx : 1; 151 uint32_t only_null_delim_sent : 1, 152 null_delim_inserted_before_mpdus : 1, 153 fes_in_11ax_trigger_response_config : 1, 154 phytx_abort_request_info_valid : 1, 155 phytx_pkt_end_info_valid : 1, 156 reserved_1a : 6, 157 brp_info_valid : 1, 158 reserved_after_struct16 : 4; 159 struct phytx_abort_request_info phytx_abort_request_info_details; 160 uint32_t start_of_frame_timestamp_31_16 : 16, 161 start_of_frame_timestamp_15_0 : 16; 162 uint32_t end_of_frame_timestamp_31_16 : 16, 163 end_of_frame_timestamp_15_0 : 16; 164 uint32_t transmit_delay : 16, 165 r2r_end_status_to_follow : 1, 166 response_type : 5, 167 timing_status : 2, 168 reserved_4a : 7, 169 terminate_ranging_sequence : 1; 170 uint32_t tpc_dbg_info_cmn_15_0 : 16, 171 reserved_5a : 4, 172 tx_group_delay : 12; 173 uint32_t tpc_dbg_info_47_32 : 16, 174 tpc_dbg_info_cmn_31_16 : 16; 175 uint32_t tpc_dbg_info_chn1_31_16 : 16, 176 tpc_dbg_info_chn1_15_0 : 16; 177 uint32_t tpc_dbg_info_chn1_63_48 : 16, 178 tpc_dbg_info_chn1_47_32 : 16; 179 uint32_t tpc_dbg_info_chn2_15_0 : 16, 180 tpc_dbg_info_chn1_79_64 : 16; 181 uint32_t tpc_dbg_info_chn2_47_32 : 16, 182 tpc_dbg_info_chn2_31_16 : 16; 183 uint32_t tpc_dbg_info_chn2_79_64 : 16, 184 tpc_dbg_info_chn2_63_48 : 16; 185 uint32_t phytx_tx_end_sw_info_31_16 : 16, 186 phytx_tx_end_sw_info_15_0 : 16; 187 uint32_t phytx_tx_end_sw_info_63_48 : 16, 188 phytx_tx_end_sw_info_47_32 : 16; 189 uint32_t beamform_masked_user_bitmap_31_16 : 16, 190 beamform_masked_user_bitmap_15_0 : 16; 191 uint32_t pdg_mpdu_ready : 1, 192 beamform_masked_user_bitmap_36_32 : 5, 193 obss_pd_based_transmit_status : 1, 194 srp_based_transmit_status : 1, 195 obss_srg_opport_transmit_status : 1, 196 static_2_pwr_mode_status : 1, 197 use_alt_power_sr : 1, 198 highest_achieved_data_null_ratio : 5, 199 cbf_segment_sent_mask : 8, 200 cbf_segment_request_mask : 8; 201 uint32_t pdg_est_mpdu_tx_count : 16, 202 pdg_mpdu_count : 16; 203 uint32_t pdg_dropped_mpdu_warning : 1, 204 txop_duration : 7, 205 pdg_overview_length : 24; 206 uint32_t reserved_17a : 4, 207 ru_size : 4, 208 num_data_symbols : 16, 209 stbc : 1, 210 fec_type : 1, 211 packet_extension : 3, 212 packet_extension_pe_disambiguity : 1, 213 packet_extension_a_factor : 2; 214 uint32_t tx_pwr_unshared : 8, 215 tx_pwr_shared : 8, 216 reserved_18b : 1, 217 force_extra_symbol : 1, 218 ldpc_extra_symbol : 1, 219 dcm : 1, 220 reserved_18a : 5, 221 cp_setting : 2, 222 ltf_size : 2, 223 num_ltf_symbols : 3; 224 uint32_t cv_corr_status : 8, 225 reserved_20a : 6, 226 ranging_ftm_frame_sent : 1, 227 ranging_sent_dummy_tx : 1, 228 ranging_active_user_map : 16; 229 uint32_t reserved_21a : 16, 230 current_tx_duration : 16; 231 #endif 232 }; 233 234 235 236 237 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 238 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 239 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 240 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 241 242 243 244 245 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 246 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 247 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 248 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000002 249 250 251 252 253 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 254 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 255 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 256 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 257 258 259 260 261 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 262 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 263 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 264 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000008 265 266 267 268 269 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 270 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 271 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 272 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000010 273 274 275 276 277 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 278 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 279 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 280 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000020 281 282 283 284 285 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 286 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 287 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 288 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000040 289 290 291 292 293 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 294 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 295 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 296 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000080 297 298 299 300 301 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 302 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 303 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 304 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000100 305 306 307 308 309 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 310 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 311 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 312 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000200 313 314 315 316 317 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 318 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 319 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 320 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000400 321 322 323 324 325 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 326 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 327 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 328 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000800 329 330 331 332 333 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 334 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 335 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 336 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 337 338 339 340 341 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 342 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 343 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 344 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 345 346 347 348 349 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 350 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 351 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 352 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 353 354 355 356 357 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 358 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 359 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 360 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 361 362 363 364 365 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 366 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 367 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 368 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 369 370 371 372 373 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 374 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 375 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 376 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 377 378 379 380 381 #define TX_FES_STATUS_END_DPDTRAIN_DONE_OFFSET 0x0000000000000000 382 #define TX_FES_STATUS_END_DPDTRAIN_DONE_LSB 31 383 #define TX_FES_STATUS_END_DPDTRAIN_DONE_MSB 31 384 #define TX_FES_STATUS_END_DPDTRAIN_DONE_MASK 0x0000000080000000 385 386 387 388 389 390 391 392 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 393 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 394 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 395 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 396 397 398 399 400 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 401 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 402 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 403 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 404 405 406 407 408 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 409 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 410 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 411 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 412 413 414 415 416 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 417 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 418 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 419 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 420 421 422 423 424 #define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 425 #define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 426 #define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 427 #define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 428 429 430 431 432 #define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 433 #define TX_FES_STATUS_END_RESERVED_1A_LSB 53 434 #define TX_FES_STATUS_END_RESERVED_1A_MSB 58 435 #define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07e0000000000000 436 437 438 439 440 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 441 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 442 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 443 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 444 445 446 447 448 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 449 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 450 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 451 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 452 453 454 455 456 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 457 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 458 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 459 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 460 461 462 463 464 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 465 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 466 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 467 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 468 469 470 471 472 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 473 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 474 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 475 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 476 477 478 479 480 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 481 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 482 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 483 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 484 485 486 487 488 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 489 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 490 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 491 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 492 493 494 495 496 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 497 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 498 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 499 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 500 501 502 503 504 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 505 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 506 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 507 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 508 509 510 511 512 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x0000000000000010 513 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 514 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 515 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x0000000000000001 516 517 518 519 520 #define TX_FES_STATUS_END_RESERVED_4A_OFFSET 0x0000000000000010 521 #define TX_FES_STATUS_END_RESERVED_4A_LSB 1 522 #define TX_FES_STATUS_END_RESERVED_4A_MSB 7 523 #define TX_FES_STATUS_END_RESERVED_4A_MASK 0x00000000000000fe 524 525 526 527 528 #define TX_FES_STATUS_END_TIMING_STATUS_OFFSET 0x0000000000000010 529 #define TX_FES_STATUS_END_TIMING_STATUS_LSB 8 530 #define TX_FES_STATUS_END_TIMING_STATUS_MSB 9 531 #define TX_FES_STATUS_END_TIMING_STATUS_MASK 0x0000000000000300 532 533 534 535 536 #define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000010 537 #define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 10 538 #define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 14 539 #define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x0000000000007c00 540 541 542 543 544 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000010 545 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 15 546 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 15 547 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000008000 548 549 550 551 552 #define TX_FES_STATUS_END_TRANSMIT_DELAY_OFFSET 0x0000000000000010 553 #define TX_FES_STATUS_END_TRANSMIT_DELAY_LSB 16 554 #define TX_FES_STATUS_END_TRANSMIT_DELAY_MSB 31 555 #define TX_FES_STATUS_END_TRANSMIT_DELAY_MASK 0x00000000ffff0000 556 557 558 559 560 #define TX_FES_STATUS_END_TX_GROUP_DELAY_OFFSET 0x0000000000000010 561 #define TX_FES_STATUS_END_TX_GROUP_DELAY_LSB 32 562 #define TX_FES_STATUS_END_TX_GROUP_DELAY_MSB 43 563 #define TX_FES_STATUS_END_TX_GROUP_DELAY_MASK 0x00000fff00000000 564 565 566 567 568 #define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000010 569 #define TX_FES_STATUS_END_RESERVED_5A_LSB 44 570 #define TX_FES_STATUS_END_RESERVED_5A_MSB 47 571 #define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000f00000000000 572 573 574 575 576 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 577 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_LSB 48 578 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MSB 63 579 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 580 581 582 583 584 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000018 585 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_LSB 0 586 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MSB 15 587 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MASK 0x000000000000ffff 588 589 590 591 592 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000018 593 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_LSB 16 594 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MSB 31 595 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 596 597 598 599 600 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 601 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_LSB 32 602 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MSB 47 603 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 604 605 606 607 608 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 609 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_LSB 48 610 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MSB 63 611 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 612 613 614 615 616 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000020 617 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 618 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 619 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff 620 621 622 623 624 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 625 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_LSB 16 626 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MSB 31 627 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 628 629 630 631 632 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 633 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_LSB 32 634 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MSB 47 635 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 636 637 638 639 640 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 641 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_LSB 48 642 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MSB 63 643 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 644 645 646 647 648 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000028 649 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 650 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 651 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff 652 653 654 655 656 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 657 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_LSB 16 658 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MSB 31 659 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 660 661 662 663 664 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 665 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_LSB 32 666 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MSB 47 667 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 668 669 670 671 672 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 673 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_LSB 48 674 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MSB 63 675 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 676 677 678 679 680 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 681 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 682 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 683 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 684 685 686 687 688 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 689 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_LSB 16 690 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MSB 31 691 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 692 693 694 695 696 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 697 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_LSB 32 698 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MSB 47 699 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 700 701 702 703 704 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 705 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_LSB 48 706 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MSB 63 707 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 708 709 710 711 712 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000038 713 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 714 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 715 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x000000000000ffff 716 717 718 719 720 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000038 721 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 722 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 723 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x00000000ffff0000 724 725 726 727 728 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000038 729 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 32 730 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 39 731 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff00000000 732 733 734 735 736 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000038 737 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 40 738 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 47 739 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff0000000000 740 741 742 743 744 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000038 745 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 48 746 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 52 747 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f000000000000 748 749 750 751 752 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000038 753 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 53 754 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 53 755 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0020000000000000 756 757 758 759 760 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000038 761 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 54 762 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 54 763 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0040000000000000 764 765 766 767 768 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000038 769 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 55 770 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 55 771 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0080000000000000 772 773 774 775 776 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 777 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 56 778 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 56 779 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0100000000000000 780 781 782 783 784 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 785 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 57 786 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 57 787 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0200000000000000 788 789 790 791 792 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000038 793 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 58 794 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 62 795 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c00000000000000 796 797 798 799 800 #define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000038 801 #define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 63 802 #define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 63 803 #define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x8000000000000000 804 805 806 807 808 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000040 809 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 810 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 811 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x000000000000ffff 812 813 814 815 816 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000040 817 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 818 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 819 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0x00000000ffff0000 820 821 822 823 824 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000040 825 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 32 826 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 55 827 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff00000000 828 829 830 831 832 #define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000040 833 #define TX_FES_STATUS_END_TXOP_DURATION_LSB 56 834 #define TX_FES_STATUS_END_TXOP_DURATION_MSB 62 835 #define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f00000000000000 836 837 838 839 840 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000040 841 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 63 842 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 63 843 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x8000000000000000 844 845 846 847 848 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000048 849 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 850 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 851 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 852 853 854 855 856 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000048 857 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 858 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 859 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 860 861 862 863 864 #define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000048 865 #define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 866 #define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 867 #define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000000000000038 868 869 870 871 872 #define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000048 873 #define TX_FES_STATUS_END_FEC_TYPE_LSB 6 874 #define TX_FES_STATUS_END_FEC_TYPE_MSB 6 875 #define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000000000000040 876 877 878 879 880 #define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000048 881 #define TX_FES_STATUS_END_STBC_LSB 7 882 #define TX_FES_STATUS_END_STBC_MSB 7 883 #define TX_FES_STATUS_END_STBC_MASK 0x0000000000000080 884 885 886 887 888 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000048 889 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 890 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 891 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x0000000000ffff00 892 893 894 895 896 #define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000048 897 #define TX_FES_STATUS_END_RU_SIZE_LSB 24 898 #define TX_FES_STATUS_END_RU_SIZE_MSB 27 899 #define TX_FES_STATUS_END_RU_SIZE_MASK 0x000000000f000000 900 901 902 903 904 #define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000048 905 #define TX_FES_STATUS_END_RESERVED_17A_LSB 28 906 #define TX_FES_STATUS_END_RESERVED_17A_MSB 31 907 #define TX_FES_STATUS_END_RESERVED_17A_MASK 0x00000000f0000000 908 909 910 911 912 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000048 913 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 32 914 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 34 915 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 916 917 918 919 920 #define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000048 921 #define TX_FES_STATUS_END_LTF_SIZE_LSB 35 922 #define TX_FES_STATUS_END_LTF_SIZE_MSB 36 923 #define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000001800000000 924 925 926 927 928 #define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000048 929 #define TX_FES_STATUS_END_CP_SETTING_LSB 37 930 #define TX_FES_STATUS_END_CP_SETTING_MSB 38 931 #define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000006000000000 932 933 934 935 936 #define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000048 937 #define TX_FES_STATUS_END_RESERVED_18A_LSB 39 938 #define TX_FES_STATUS_END_RESERVED_18A_MSB 43 939 #define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f8000000000 940 941 942 943 944 #define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000048 945 #define TX_FES_STATUS_END_DCM_LSB 44 946 #define TX_FES_STATUS_END_DCM_MSB 44 947 #define TX_FES_STATUS_END_DCM_MASK 0x0000100000000000 948 949 950 951 952 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000048 953 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 45 954 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 45 955 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000200000000000 956 957 958 959 960 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 961 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 46 962 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 46 963 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000400000000000 964 965 966 967 968 #define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000048 969 #define TX_FES_STATUS_END_RESERVED_18B_LSB 47 970 #define TX_FES_STATUS_END_RESERVED_18B_MSB 47 971 #define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000800000000000 972 973 974 975 976 #define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000048 977 #define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 48 978 #define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 55 979 #define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff000000000000 980 981 982 983 984 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000048 985 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 56 986 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 63 987 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff00000000000000 988 989 990 991 992 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x0000000000000050 993 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 994 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 995 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x000000000000ffff 996 997 998 999 1000 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x0000000000000050 1001 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 1002 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 1003 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x0000000000010000 1004 1005 1006 1007 1008 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 1009 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 1010 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 1011 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x0000000000020000 1012 1013 1014 1015 1016 #define TX_FES_STATUS_END_RESERVED_20A_OFFSET 0x0000000000000050 1017 #define TX_FES_STATUS_END_RESERVED_20A_LSB 18 1018 #define TX_FES_STATUS_END_RESERVED_20A_MSB 23 1019 #define TX_FES_STATUS_END_RESERVED_20A_MASK 0x0000000000fc0000 1020 1021 1022 1023 1024 #define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000050 1025 #define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 1026 #define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 1027 #define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0x00000000ff000000 1028 1029 1030 1031 1032 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000050 1033 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 32 1034 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 47 1035 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff00000000 1036 1037 1038 1039 1040 #define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000050 1041 #define TX_FES_STATUS_END_RESERVED_21A_LSB 48 1042 #define TX_FES_STATUS_END_RESERVED_21A_MSB 63 1043 #define TX_FES_STATUS_END_RESERVED_21A_MASK 0xffff000000000000 1044 1045 1046 1047 #endif 1048