1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TX_FES_STATUS_PROT_H_ 20 #define _TX_FES_STATUS_PROT_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "phytx_abort_request_info.h" 25 #define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14 26 27 #define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7 28 29 30 struct tx_fes_status_prot { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t success : 1, 33 phytx_pkt_end_info_valid : 1, 34 phytx_abort_request_info_valid : 1, 35 reserved_0 : 20, 36 pkt_type : 4, 37 dot11ax_su_extended : 1, 38 rate_mcs : 4; 39 uint32_t frame_type : 2, 40 frame_subtype : 4, 41 rx_pwr_mgmt : 1, 42 status : 1, 43 duration_field : 16, 44 reserved_1a : 2, 45 agc_cbw : 3, 46 service_cbw : 3; 47 uint32_t start_of_frame_timestamp_15_0 : 16, 48 start_of_frame_timestamp_31_16 : 16; 49 uint32_t end_of_frame_timestamp_15_0 : 16, 50 end_of_frame_timestamp_31_16 : 16; 51 uint32_t tx_group_delay : 12, 52 timing_status : 2, 53 dpdtrain_done : 1, 54 reserved_4 : 1, 55 transmit_delay : 16; 56 uint32_t tpc_dbg_info_cmn_15_0 : 16, 57 tpc_dbg_info_cmn_31_16 : 16; 58 uint32_t tpc_dbg_info_cmn_47_32 : 16, 59 tpc_dbg_info_chn1_15_0 : 16; 60 uint32_t tpc_dbg_info_chn1_31_16 : 16, 61 tpc_dbg_info_chn1_47_32 : 16; 62 uint32_t tpc_dbg_info_chn1_63_48 : 16, 63 tpc_dbg_info_chn1_79_64 : 16; 64 uint32_t tpc_dbg_info_chn2_15_0 : 16, 65 tpc_dbg_info_chn2_31_16 : 16; 66 uint32_t tpc_dbg_info_chn2_47_32 : 16, 67 tpc_dbg_info_chn2_63_48 : 16; 68 uint32_t tpc_dbg_info_chn2_79_64 : 16; 69 struct phytx_abort_request_info phytx_abort_request_info_details; 70 uint32_t phytx_tx_end_sw_info_15_0 : 16, 71 phytx_tx_end_sw_info_31_16 : 16; 72 uint32_t phytx_tx_end_sw_info_47_32 : 16, 73 phytx_tx_end_sw_info_63_48 : 16; 74 #else 75 uint32_t rate_mcs : 4, 76 dot11ax_su_extended : 1, 77 pkt_type : 4, 78 reserved_0 : 20, 79 phytx_abort_request_info_valid : 1, 80 phytx_pkt_end_info_valid : 1, 81 success : 1; 82 uint32_t service_cbw : 3, 83 agc_cbw : 3, 84 reserved_1a : 2, 85 duration_field : 16, 86 status : 1, 87 rx_pwr_mgmt : 1, 88 frame_subtype : 4, 89 frame_type : 2; 90 uint32_t start_of_frame_timestamp_31_16 : 16, 91 start_of_frame_timestamp_15_0 : 16; 92 uint32_t end_of_frame_timestamp_31_16 : 16, 93 end_of_frame_timestamp_15_0 : 16; 94 uint32_t transmit_delay : 16, 95 reserved_4 : 1, 96 dpdtrain_done : 1, 97 timing_status : 2, 98 tx_group_delay : 12; 99 uint32_t tpc_dbg_info_cmn_31_16 : 16, 100 tpc_dbg_info_cmn_15_0 : 16; 101 uint32_t tpc_dbg_info_chn1_15_0 : 16, 102 tpc_dbg_info_cmn_47_32 : 16; 103 uint32_t tpc_dbg_info_chn1_47_32 : 16, 104 tpc_dbg_info_chn1_31_16 : 16; 105 uint32_t tpc_dbg_info_chn1_79_64 : 16, 106 tpc_dbg_info_chn1_63_48 : 16; 107 uint32_t tpc_dbg_info_chn2_31_16 : 16, 108 tpc_dbg_info_chn2_15_0 : 16; 109 uint32_t tpc_dbg_info_chn2_63_48 : 16, 110 tpc_dbg_info_chn2_47_32 : 16; 111 struct phytx_abort_request_info phytx_abort_request_info_details; 112 uint16_t tpc_dbg_info_chn2_79_64 : 16; 113 uint32_t phytx_tx_end_sw_info_31_16 : 16, 114 phytx_tx_end_sw_info_15_0 : 16; 115 uint32_t phytx_tx_end_sw_info_63_48 : 16, 116 phytx_tx_end_sw_info_47_32 : 16; 117 #endif 118 }; 119 120 121 122 123 #define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 124 #define TX_FES_STATUS_PROT_SUCCESS_LSB 0 125 #define TX_FES_STATUS_PROT_SUCCESS_MSB 0 126 #define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 127 128 129 130 131 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 132 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 133 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 134 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 135 136 137 138 139 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 140 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 141 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 142 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 143 144 145 146 147 #define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 148 #define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 149 #define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 150 #define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8 151 152 153 154 155 #define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 156 #define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 157 #define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 158 #define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000 159 160 161 162 163 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 164 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 165 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 166 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000 167 168 169 170 171 #define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 172 #define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 173 #define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 174 #define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000 175 176 177 178 179 #define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 180 #define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 181 #define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 182 #define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 183 184 185 186 187 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 188 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 189 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 190 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 191 192 193 194 195 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 196 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 197 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 198 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 199 200 201 202 203 #define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 204 #define TX_FES_STATUS_PROT_STATUS_LSB 39 205 #define TX_FES_STATUS_PROT_STATUS_MSB 39 206 #define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 207 208 209 210 211 #define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 212 #define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 213 #define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 214 #define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 215 216 217 218 219 #define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 220 #define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 221 #define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 222 #define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 223 224 225 226 227 #define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 228 #define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 229 #define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 230 #define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 231 232 233 234 235 #define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 236 #define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 237 #define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 238 #define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 239 240 241 242 243 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 244 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 245 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 246 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 247 248 249 250 251 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 252 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 253 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 254 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 255 256 257 258 259 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 260 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 261 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 262 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 263 264 265 266 267 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 268 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 269 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 270 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 271 272 273 274 275 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010 276 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0 277 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11 278 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff 279 280 281 282 283 #define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010 284 #define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12 285 #define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13 286 #define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000 287 288 289 290 291 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010 292 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14 293 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14 294 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000 295 296 297 298 299 #define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010 300 #define TX_FES_STATUS_PROT_RESERVED_4_LSB 15 301 #define TX_FES_STATUS_PROT_RESERVED_4_MSB 15 302 #define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000 303 304 305 306 307 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010 308 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16 309 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31 310 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000 311 312 313 314 315 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 316 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32 317 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47 318 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000 319 320 321 322 323 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010 324 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48 325 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63 326 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000 327 328 329 330 331 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018 332 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0 333 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15 334 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff 335 336 337 338 339 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 340 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16 341 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31 342 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000 343 344 345 346 347 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 348 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32 349 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47 350 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000 351 352 353 354 355 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018 356 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48 357 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63 358 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000 359 360 361 362 363 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 364 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0 365 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15 366 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff 367 368 369 370 371 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 372 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16 373 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31 374 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000 375 376 377 378 379 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 380 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32 381 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47 382 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000 383 384 385 386 387 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020 388 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48 389 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63 390 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000 391 392 393 394 395 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 396 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0 397 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15 398 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff 399 400 401 402 403 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 404 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16 405 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31 406 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000 407 408 409 410 411 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 412 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32 413 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47 414 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000 415 416 417 418 419 420 421 422 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028 423 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48 424 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55 425 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000 426 427 428 429 430 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028 431 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56 432 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61 433 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000 434 435 436 437 438 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028 439 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62 440 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63 441 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000 442 443 444 445 446 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 447 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0 448 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15 449 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 450 451 452 453 454 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 455 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16 456 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31 457 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 458 459 460 461 462 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 463 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32 464 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47 465 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 466 467 468 469 470 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 471 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48 472 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63 473 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 474 475 476 477 #endif 478