1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TX_FES_STATUS_USER_PPDU_H_ 20 #define _TX_FES_STATUS_USER_PPDU_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 25 26 #define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 27 28 29 struct tx_fes_status_user_ppdu { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t underflow_mpdu_count : 9, 32 data_underflow_warning : 2, 33 bw_drop_underflow_warning : 1, 34 qc_eosp_setting : 1, 35 fc_more_data_setting : 1, 36 fc_pwr_mgt_setting : 1, 37 mpdu_tx_count : 9, 38 user_blocked : 1, 39 pre_trig_response_delim_count : 7; 40 uint32_t underflow_byte_count : 16, 41 coex_abort_mpdu_count_valid : 1, 42 coex_abort_mpdu_count : 9, 43 transmitted_tid : 4, 44 txdma_dropped_mpdu_warning : 1, 45 reserved_1 : 1; 46 uint32_t duration : 16, 47 num_eof_delim_added : 16; 48 uint32_t psdu_octet : 24, 49 qos_buf_state : 8; 50 uint32_t num_null_delim_added : 22, 51 reserved_4a : 2, 52 cv_corr_user_valid_in_phy : 1, 53 nss : 3, 54 mcs : 4; 55 uint32_t ht_control : 32; 56 #else 57 uint32_t pre_trig_response_delim_count : 7, 58 user_blocked : 1, 59 mpdu_tx_count : 9, 60 fc_pwr_mgt_setting : 1, 61 fc_more_data_setting : 1, 62 qc_eosp_setting : 1, 63 bw_drop_underflow_warning : 1, 64 data_underflow_warning : 2, 65 underflow_mpdu_count : 9; 66 uint32_t reserved_1 : 1, 67 txdma_dropped_mpdu_warning : 1, 68 transmitted_tid : 4, 69 coex_abort_mpdu_count : 9, 70 coex_abort_mpdu_count_valid : 1, 71 underflow_byte_count : 16; 72 uint32_t num_eof_delim_added : 16, 73 duration : 16; 74 uint32_t qos_buf_state : 8, 75 psdu_octet : 24; 76 uint32_t mcs : 4, 77 nss : 3, 78 cv_corr_user_valid_in_phy : 1, 79 reserved_4a : 2, 80 num_null_delim_added : 22; 81 uint32_t ht_control : 32; 82 #endif 83 }; 84 85 86 87 88 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 89 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 90 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 91 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff 92 93 94 95 96 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 97 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 98 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 99 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 100 101 102 103 104 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 105 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 106 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 107 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 108 109 110 111 112 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 113 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 114 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 115 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 116 117 118 119 120 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 121 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 122 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 123 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000002000 124 125 126 127 128 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 129 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 130 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 131 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000004000 132 133 134 135 136 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 137 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 138 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 139 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ff8000 140 141 142 143 144 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 145 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 146 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 147 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 148 149 150 151 152 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 153 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 154 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 155 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 156 157 158 159 160 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 161 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 162 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 163 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 164 165 166 167 168 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 169 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 170 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 171 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 172 173 174 175 176 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 177 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 178 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 179 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 180 181 182 183 184 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 185 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 186 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 187 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 188 189 190 191 192 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 193 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 194 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 195 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 196 197 198 199 200 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x0000000000000000 201 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 63 202 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 63 203 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x8000000000000000 204 205 206 207 208 #define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 209 #define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 210 #define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 211 #define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff 212 213 214 215 216 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 217 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 218 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 219 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 220 221 222 223 224 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 225 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 226 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 227 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 228 229 230 231 232 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 233 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 234 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 235 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 236 237 238 239 240 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 241 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 242 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 243 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff 244 245 246 247 248 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 249 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 250 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 251 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x0000000000c00000 252 253 254 255 256 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000010 257 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 258 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 259 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x0000000001000000 260 261 262 263 264 #define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 265 #define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 266 #define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 267 #define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x000000000e000000 268 269 270 271 272 #define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 273 #define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 274 #define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 275 #define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f0000000 276 277 278 279 280 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 281 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 282 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 283 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 284 285 286 287 #endif 288