1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TX_MPDU_START_H_ 20 #define _TX_MPDU_START_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TX_MPDU_START 10 25 26 #define NUM_OF_QWORDS_TX_MPDU_START 5 27 28 29 struct tx_mpdu_start { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t mpdu_length : 14, 32 frame_not_from_tqm : 1, 33 vht_control_present : 1, 34 mpdu_header_length : 8, 35 retry_count : 7, 36 wds : 1; 37 uint32_t pn_31_0 : 32; 38 uint32_t pn_47_32 : 16, 39 mpdu_sequence_number : 12, 40 raw_already_encrypted : 1, 41 frame_type : 2, 42 txdma_dropped_mpdu_warning : 1; 43 uint32_t iv_byte_0 : 8, 44 iv_byte_1 : 8, 45 iv_byte_2 : 8, 46 iv_byte_3 : 8; 47 uint32_t iv_byte_4 : 8, 48 iv_byte_5 : 8, 49 iv_byte_6 : 8, 50 iv_byte_7 : 8; 51 uint32_t iv_byte_8 : 8, 52 iv_byte_9 : 8, 53 iv_byte_10 : 8, 54 iv_byte_11 : 8; 55 uint32_t iv_byte_12 : 8, 56 iv_byte_13 : 8, 57 iv_byte_14 : 8, 58 iv_byte_15 : 8; 59 uint32_t iv_byte_16 : 8, 60 iv_byte_17 : 8, 61 iv_len : 5, 62 icv_len : 5, 63 vht_control_offset : 6; 64 uint32_t mpdu_type : 1, 65 transmit_bw_restriction : 1, 66 allowed_transmit_bw : 4, 67 tx_notify_frame : 3, 68 reserved_8a : 23; 69 uint32_t tlv64_padding : 32; 70 #else 71 uint32_t wds : 1, 72 retry_count : 7, 73 mpdu_header_length : 8, 74 vht_control_present : 1, 75 frame_not_from_tqm : 1, 76 mpdu_length : 14; 77 uint32_t pn_31_0 : 32; 78 uint32_t txdma_dropped_mpdu_warning : 1, 79 frame_type : 2, 80 raw_already_encrypted : 1, 81 mpdu_sequence_number : 12, 82 pn_47_32 : 16; 83 uint32_t iv_byte_3 : 8, 84 iv_byte_2 : 8, 85 iv_byte_1 : 8, 86 iv_byte_0 : 8; 87 uint32_t iv_byte_7 : 8, 88 iv_byte_6 : 8, 89 iv_byte_5 : 8, 90 iv_byte_4 : 8; 91 uint32_t iv_byte_11 : 8, 92 iv_byte_10 : 8, 93 iv_byte_9 : 8, 94 iv_byte_8 : 8; 95 uint32_t iv_byte_15 : 8, 96 iv_byte_14 : 8, 97 iv_byte_13 : 8, 98 iv_byte_12 : 8; 99 uint32_t vht_control_offset : 6, 100 icv_len : 5, 101 iv_len : 5, 102 iv_byte_17 : 8, 103 iv_byte_16 : 8; 104 uint32_t reserved_8a : 23, 105 tx_notify_frame : 3, 106 allowed_transmit_bw : 4, 107 transmit_bw_restriction : 1, 108 mpdu_type : 1; 109 uint32_t tlv64_padding : 32; 110 #endif 111 }; 112 113 114 115 116 #define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 117 #define TX_MPDU_START_MPDU_LENGTH_LSB 0 118 #define TX_MPDU_START_MPDU_LENGTH_MSB 13 119 #define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff 120 121 122 123 124 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 125 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 126 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 127 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 128 129 130 131 132 #define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 133 #define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 134 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 135 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 136 137 138 139 140 #define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 141 #define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 142 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 143 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 144 145 146 147 148 #define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 149 #define TX_MPDU_START_RETRY_COUNT_LSB 24 150 #define TX_MPDU_START_RETRY_COUNT_MSB 30 151 #define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 152 153 154 155 156 #define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 157 #define TX_MPDU_START_WDS_LSB 31 158 #define TX_MPDU_START_WDS_MSB 31 159 #define TX_MPDU_START_WDS_MASK 0x0000000080000000 160 161 162 163 164 #define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 165 #define TX_MPDU_START_PN_31_0_LSB 32 166 #define TX_MPDU_START_PN_31_0_MSB 63 167 #define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 168 169 170 171 172 #define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 173 #define TX_MPDU_START_PN_47_32_LSB 0 174 #define TX_MPDU_START_PN_47_32_MSB 15 175 #define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff 176 177 178 179 180 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 181 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 182 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 183 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 184 185 186 187 188 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 189 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 190 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 191 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 192 193 194 195 196 #define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 197 #define TX_MPDU_START_FRAME_TYPE_LSB 29 198 #define TX_MPDU_START_FRAME_TYPE_MSB 30 199 #define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 200 201 202 203 204 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 205 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 206 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 207 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 208 209 210 211 212 #define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 213 #define TX_MPDU_START_IV_BYTE_0_LSB 32 214 #define TX_MPDU_START_IV_BYTE_0_MSB 39 215 #define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 216 217 218 219 220 #define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 221 #define TX_MPDU_START_IV_BYTE_1_LSB 40 222 #define TX_MPDU_START_IV_BYTE_1_MSB 47 223 #define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 224 225 226 227 228 #define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 229 #define TX_MPDU_START_IV_BYTE_2_LSB 48 230 #define TX_MPDU_START_IV_BYTE_2_MSB 55 231 #define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 232 233 234 235 236 #define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 237 #define TX_MPDU_START_IV_BYTE_3_LSB 56 238 #define TX_MPDU_START_IV_BYTE_3_MSB 63 239 #define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 240 241 242 243 244 #define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 245 #define TX_MPDU_START_IV_BYTE_4_LSB 0 246 #define TX_MPDU_START_IV_BYTE_4_MSB 7 247 #define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff 248 249 250 251 252 #define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 253 #define TX_MPDU_START_IV_BYTE_5_LSB 8 254 #define TX_MPDU_START_IV_BYTE_5_MSB 15 255 #define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 256 257 258 259 260 #define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 261 #define TX_MPDU_START_IV_BYTE_6_LSB 16 262 #define TX_MPDU_START_IV_BYTE_6_MSB 23 263 #define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 264 265 266 267 268 #define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 269 #define TX_MPDU_START_IV_BYTE_7_LSB 24 270 #define TX_MPDU_START_IV_BYTE_7_MSB 31 271 #define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 272 273 274 275 276 #define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 277 #define TX_MPDU_START_IV_BYTE_8_LSB 32 278 #define TX_MPDU_START_IV_BYTE_8_MSB 39 279 #define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 280 281 282 283 284 #define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 285 #define TX_MPDU_START_IV_BYTE_9_LSB 40 286 #define TX_MPDU_START_IV_BYTE_9_MSB 47 287 #define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 288 289 290 291 292 #define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 293 #define TX_MPDU_START_IV_BYTE_10_LSB 48 294 #define TX_MPDU_START_IV_BYTE_10_MSB 55 295 #define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 296 297 298 299 300 #define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 301 #define TX_MPDU_START_IV_BYTE_11_LSB 56 302 #define TX_MPDU_START_IV_BYTE_11_MSB 63 303 #define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 304 305 306 307 308 #define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 309 #define TX_MPDU_START_IV_BYTE_12_LSB 0 310 #define TX_MPDU_START_IV_BYTE_12_MSB 7 311 #define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff 312 313 314 315 316 #define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 317 #define TX_MPDU_START_IV_BYTE_13_LSB 8 318 #define TX_MPDU_START_IV_BYTE_13_MSB 15 319 #define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 320 321 322 323 324 #define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 325 #define TX_MPDU_START_IV_BYTE_14_LSB 16 326 #define TX_MPDU_START_IV_BYTE_14_MSB 23 327 #define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 328 329 330 331 332 #define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 333 #define TX_MPDU_START_IV_BYTE_15_LSB 24 334 #define TX_MPDU_START_IV_BYTE_15_MSB 31 335 #define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 336 337 338 339 340 #define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 341 #define TX_MPDU_START_IV_BYTE_16_LSB 32 342 #define TX_MPDU_START_IV_BYTE_16_MSB 39 343 #define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 344 345 346 347 348 #define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 349 #define TX_MPDU_START_IV_BYTE_17_LSB 40 350 #define TX_MPDU_START_IV_BYTE_17_MSB 47 351 #define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 352 353 354 355 356 #define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 357 #define TX_MPDU_START_IV_LEN_LSB 48 358 #define TX_MPDU_START_IV_LEN_MSB 52 359 #define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 360 361 362 363 364 #define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 365 #define TX_MPDU_START_ICV_LEN_LSB 53 366 #define TX_MPDU_START_ICV_LEN_MSB 57 367 #define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 368 369 370 371 372 #define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 373 #define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 374 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 375 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 376 377 378 379 380 #define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 381 #define TX_MPDU_START_MPDU_TYPE_LSB 0 382 #define TX_MPDU_START_MPDU_TYPE_MSB 0 383 #define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 384 385 386 387 388 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 389 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 390 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 391 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 392 393 394 395 396 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 397 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 398 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 399 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c 400 401 402 403 404 #define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 405 #define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 406 #define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 407 #define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 408 409 410 411 412 #define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 413 #define TX_MPDU_START_RESERVED_8A_LSB 9 414 #define TX_MPDU_START_RESERVED_8A_MSB 31 415 #define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 416 417 418 419 420 #define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 421 #define TX_MPDU_START_TLV64_PADDING_LSB 32 422 #define TX_MPDU_START_TLV64_PADDING_MSB 63 423 #define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 424 425 426 427 #endif 428