xref: /wlan-driver/fw-api/hw/qca5424/tx_peer_entry.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /*
3  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4  * SPDX-License-Identifier: ISC
5  */
6 
7 
8 
9 
10 
11 
12 
13 
14 
15 
16 
17 
18 
19 #ifndef _TX_PEER_ENTRY_H_
20 #define _TX_PEER_ENTRY_H_
21 #if !defined(__ASSEMBLER__)
22 #endif
23 
24 #define NUM_OF_DWORDS_TX_PEER_ENTRY 18
25 
26 #define NUM_OF_QWORDS_TX_PEER_ENTRY 9
27 
28 
29 struct tx_peer_entry {
30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
31              uint32_t mac_addr_a_31_0                                         : 32;
32              uint32_t mac_addr_a_47_32                                        : 16,
33                       mac_addr_b_15_0                                         : 16;
34              uint32_t mac_addr_b_47_16                                        : 32;
35              uint32_t use_ad_b                                                :  1,
36                       strip_insert_vlan_inner                                 :  1,
37                       strip_insert_vlan_outer                                 :  1,
38                       vlan_llc_mode                                           :  1,
39                       key_type                                                :  4,
40                       a_msdu_wds_ad3_ad4                                      :  3,
41                       ignore_hard_filters                                     :  1,
42                       ignore_soft_filters                                     :  1,
43                       epd_output                                              :  1,
44                       wds                                                     :  1,
45                       insert_or_strip                                         :  1,
46                       sw_filter_id                                            : 16;
47              uint32_t temporal_key_31_0                                       : 32;
48              uint32_t temporal_key_63_32                                      : 32;
49              uint32_t temporal_key_95_64                                      : 32;
50              uint32_t temporal_key_127_96                                     : 32;
51              uint32_t temporal_key_159_128                                    : 32;
52              uint32_t temporal_key_191_160                                    : 32;
53              uint32_t temporal_key_223_192                                    : 32;
54              uint32_t temporal_key_255_224                                    : 32;
55              uint32_t sta_partial_aid                                         : 11,
56                       transmit_vif                                            :  4,
57                       block_this_user                                         :  1,
58                       mesh_amsdu_mode                                         :  2,
59                       use_qos_alt_mute_mask                                   :  1,
60                       dl_ul_direction                                         :  1,
61                       reserved_12                                             : 12;
62              uint32_t insert_vlan_outer_tci                                   : 16,
63                       insert_vlan_inner_tci                                   : 16;
64              uint32_t multi_link_addr_ad1_31_0                                : 32;
65              uint32_t multi_link_addr_ad1_47_32                               : 16,
66                       multi_link_addr_ad2_15_0                                : 16;
67              uint32_t multi_link_addr_ad2_47_16                               : 32;
68              uint32_t multi_link_addr_crypto_enable                           :  1,
69                       reserved_17a                                            : 15,
70                       sw_peer_id                                              : 16;
71 #else
72              uint32_t mac_addr_a_31_0                                         : 32;
73              uint32_t mac_addr_b_15_0                                         : 16,
74                       mac_addr_a_47_32                                        : 16;
75              uint32_t mac_addr_b_47_16                                        : 32;
76              uint32_t sw_filter_id                                            : 16,
77                       insert_or_strip                                         :  1,
78                       wds                                                     :  1,
79                       epd_output                                              :  1,
80                       ignore_soft_filters                                     :  1,
81                       ignore_hard_filters                                     :  1,
82                       a_msdu_wds_ad3_ad4                                      :  3,
83                       key_type                                                :  4,
84                       vlan_llc_mode                                           :  1,
85                       strip_insert_vlan_outer                                 :  1,
86                       strip_insert_vlan_inner                                 :  1,
87                       use_ad_b                                                :  1;
88              uint32_t temporal_key_31_0                                       : 32;
89              uint32_t temporal_key_63_32                                      : 32;
90              uint32_t temporal_key_95_64                                      : 32;
91              uint32_t temporal_key_127_96                                     : 32;
92              uint32_t temporal_key_159_128                                    : 32;
93              uint32_t temporal_key_191_160                                    : 32;
94              uint32_t temporal_key_223_192                                    : 32;
95              uint32_t temporal_key_255_224                                    : 32;
96              uint32_t reserved_12                                             : 12,
97                       dl_ul_direction                                         :  1,
98                       use_qos_alt_mute_mask                                   :  1,
99                       mesh_amsdu_mode                                         :  2,
100                       block_this_user                                         :  1,
101                       transmit_vif                                            :  4,
102                       sta_partial_aid                                         : 11;
103              uint32_t insert_vlan_inner_tci                                   : 16,
104                       insert_vlan_outer_tci                                   : 16;
105              uint32_t multi_link_addr_ad1_31_0                                : 32;
106              uint32_t multi_link_addr_ad2_15_0                                : 16,
107                       multi_link_addr_ad1_47_32                               : 16;
108              uint32_t multi_link_addr_ad2_47_16                               : 32;
109              uint32_t sw_peer_id                                              : 16,
110                       reserved_17a                                            : 15,
111                       multi_link_addr_crypto_enable                           :  1;
112 #endif
113 };
114 
115 
116 
117 
118 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET                                        0x0000000000000000
119 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB                                           0
120 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB                                           31
121 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK                                          0x00000000ffffffff
122 
123 
124 
125 
126 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET                                       0x0000000000000000
127 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB                                          32
128 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB                                          47
129 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK                                         0x0000ffff00000000
130 
131 
132 
133 
134 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET                                        0x0000000000000000
135 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB                                           48
136 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB                                           63
137 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK                                          0xffff000000000000
138 
139 
140 
141 
142 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET                                       0x0000000000000008
143 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB                                          0
144 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB                                          31
145 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK                                         0x00000000ffffffff
146 
147 
148 
149 
150 #define TX_PEER_ENTRY_USE_AD_B_OFFSET                                               0x0000000000000008
151 #define TX_PEER_ENTRY_USE_AD_B_LSB                                                  32
152 #define TX_PEER_ENTRY_USE_AD_B_MSB                                                  32
153 #define TX_PEER_ENTRY_USE_AD_B_MASK                                                 0x0000000100000000
154 
155 
156 
157 
158 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET                                0x0000000000000008
159 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB                                   33
160 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB                                   33
161 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK                                  0x0000000200000000
162 
163 
164 
165 
166 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET                                0x0000000000000008
167 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB                                   34
168 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB                                   34
169 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK                                  0x0000000400000000
170 
171 
172 
173 
174 #define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET                                          0x0000000000000008
175 #define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB                                             35
176 #define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB                                             35
177 #define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK                                            0x0000000800000000
178 
179 
180 
181 
182 #define TX_PEER_ENTRY_KEY_TYPE_OFFSET                                               0x0000000000000008
183 #define TX_PEER_ENTRY_KEY_TYPE_LSB                                                  36
184 #define TX_PEER_ENTRY_KEY_TYPE_MSB                                                  39
185 #define TX_PEER_ENTRY_KEY_TYPE_MASK                                                 0x000000f000000000
186 
187 
188 
189 
190 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET                                     0x0000000000000008
191 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB                                        40
192 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB                                        42
193 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK                                       0x0000070000000000
194 
195 
196 
197 
198 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET                                    0x0000000000000008
199 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB                                       43
200 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB                                       43
201 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK                                      0x0000080000000000
202 
203 
204 
205 
206 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET                                    0x0000000000000008
207 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB                                       44
208 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB                                       44
209 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK                                      0x0000100000000000
210 
211 
212 
213 
214 #define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET                                             0x0000000000000008
215 #define TX_PEER_ENTRY_EPD_OUTPUT_LSB                                                45
216 #define TX_PEER_ENTRY_EPD_OUTPUT_MSB                                                45
217 #define TX_PEER_ENTRY_EPD_OUTPUT_MASK                                               0x0000200000000000
218 
219 
220 
221 
222 #define TX_PEER_ENTRY_WDS_OFFSET                                                    0x0000000000000008
223 #define TX_PEER_ENTRY_WDS_LSB                                                       46
224 #define TX_PEER_ENTRY_WDS_MSB                                                       46
225 #define TX_PEER_ENTRY_WDS_MASK                                                      0x0000400000000000
226 
227 
228 
229 
230 #define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET                                        0x0000000000000008
231 #define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB                                           47
232 #define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB                                           47
233 #define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK                                          0x0000800000000000
234 
235 
236 
237 
238 #define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET                                           0x0000000000000008
239 #define TX_PEER_ENTRY_SW_FILTER_ID_LSB                                              48
240 #define TX_PEER_ENTRY_SW_FILTER_ID_MSB                                              63
241 #define TX_PEER_ENTRY_SW_FILTER_ID_MASK                                             0xffff000000000000
242 
243 
244 
245 
246 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET                                      0x0000000000000010
247 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB                                         0
248 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB                                         31
249 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK                                        0x00000000ffffffff
250 
251 
252 
253 
254 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET                                     0x0000000000000010
255 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB                                        32
256 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB                                        63
257 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK                                       0xffffffff00000000
258 
259 
260 
261 
262 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET                                     0x0000000000000018
263 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB                                        0
264 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB                                        31
265 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK                                       0x00000000ffffffff
266 
267 
268 
269 
270 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET                                    0x0000000000000018
271 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB                                       32
272 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB                                       63
273 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK                                      0xffffffff00000000
274 
275 
276 
277 
278 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET                                   0x0000000000000020
279 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB                                      0
280 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB                                      31
281 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK                                     0x00000000ffffffff
282 
283 
284 
285 
286 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET                                   0x0000000000000020
287 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB                                      32
288 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB                                      63
289 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK                                     0xffffffff00000000
290 
291 
292 
293 
294 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET                                   0x0000000000000028
295 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB                                      0
296 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB                                      31
297 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK                                     0x00000000ffffffff
298 
299 
300 
301 
302 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET                                   0x0000000000000028
303 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB                                      32
304 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB                                      63
305 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK                                     0xffffffff00000000
306 
307 
308 
309 
310 #define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET                                        0x0000000000000030
311 #define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB                                           0
312 #define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB                                           10
313 #define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK                                          0x00000000000007ff
314 
315 
316 
317 
318 #define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET                                           0x0000000000000030
319 #define TX_PEER_ENTRY_TRANSMIT_VIF_LSB                                              11
320 #define TX_PEER_ENTRY_TRANSMIT_VIF_MSB                                              14
321 #define TX_PEER_ENTRY_TRANSMIT_VIF_MASK                                             0x0000000000007800
322 
323 
324 
325 
326 #define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET                                        0x0000000000000030
327 #define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB                                           15
328 #define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB                                           15
329 #define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK                                          0x0000000000008000
330 
331 
332 
333 
334 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET                                        0x0000000000000030
335 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB                                           16
336 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB                                           17
337 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK                                          0x0000000000030000
338 
339 
340 
341 
342 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET                                  0x0000000000000030
343 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB                                     18
344 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB                                     18
345 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK                                    0x0000000000040000
346 
347 
348 
349 
350 #define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET                                        0x0000000000000030
351 #define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB                                           19
352 #define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB                                           19
353 #define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK                                          0x0000000000080000
354 
355 
356 
357 
358 #define TX_PEER_ENTRY_RESERVED_12_OFFSET                                            0x0000000000000030
359 #define TX_PEER_ENTRY_RESERVED_12_LSB                                               20
360 #define TX_PEER_ENTRY_RESERVED_12_MSB                                               31
361 #define TX_PEER_ENTRY_RESERVED_12_MASK                                              0x00000000fff00000
362 
363 
364 
365 
366 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET                                  0x0000000000000030
367 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB                                     32
368 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB                                     47
369 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK                                    0x0000ffff00000000
370 
371 
372 
373 
374 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET                                  0x0000000000000030
375 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB                                     48
376 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB                                     63
377 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK                                    0xffff000000000000
378 
379 
380 
381 
382 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_OFFSET                               0x0000000000000038
383 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_LSB                                  0
384 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MSB                                  31
385 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MASK                                 0x00000000ffffffff
386 
387 
388 
389 
390 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_OFFSET                              0x0000000000000038
391 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_LSB                                 32
392 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MSB                                 47
393 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MASK                                0x0000ffff00000000
394 
395 
396 
397 
398 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_OFFSET                               0x0000000000000038
399 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_LSB                                  48
400 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MSB                                  63
401 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MASK                                 0xffff000000000000
402 
403 
404 
405 
406 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_OFFSET                              0x0000000000000040
407 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_LSB                                 0
408 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MSB                                 31
409 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MASK                                0x00000000ffffffff
410 
411 
412 
413 
414 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET                          0x0000000000000040
415 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB                             32
416 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB                             32
417 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK                            0x0000000100000000
418 
419 
420 
421 
422 #define TX_PEER_ENTRY_RESERVED_17A_OFFSET                                           0x0000000000000040
423 #define TX_PEER_ENTRY_RESERVED_17A_LSB                                              33
424 #define TX_PEER_ENTRY_RESERVED_17A_MSB                                              47
425 #define TX_PEER_ENTRY_RESERVED_17A_MASK                                             0x0000fffe00000000
426 
427 
428 
429 
430 #define TX_PEER_ENTRY_SW_PEER_ID_OFFSET                                             0x0000000000000040
431 #define TX_PEER_ENTRY_SW_PEER_ID_LSB                                                48
432 #define TX_PEER_ENTRY_SW_PEER_ID_MSB                                                63
433 #define TX_PEER_ENTRY_SW_PEER_ID_MASK                                               0xffff000000000000
434 
435 
436 
437 #endif
438