1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TX_QUEUE_EXTENSION_H_ 20 #define _TX_QUEUE_EXTENSION_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 25 26 #define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 7 27 28 29 struct tx_queue_extension { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t frame_ctl : 16, 32 qos_ctl : 16; 33 uint32_t ampdu_flag : 1, 34 tx_notify_no_htc_override : 1, 35 reserved_1a : 7, 36 checksum_tso_disable_for_frag : 1, 37 key_id : 8, 38 qos_buf_state_overwrite : 1, 39 buf_state_sta_id : 1, 40 buf_state_source : 1, 41 ht_control_overwrite_enable : 1, 42 ht_control_overwrite_source : 4, 43 reserved_1b : 6; 44 uint32_t ul_headroom_insertion_enable : 1, 45 ul_headroom_offset : 5, 46 bqrp_insertion_enable : 1, 47 bqrp_offset : 5, 48 ul_headroom_rsvd_7_6 : 2, 49 bqr_rsvd_9_8 : 2, 50 base_pn_63_48 : 16; 51 uint32_t base_pn_95_64 : 32; 52 uint32_t base_pn_127_96 : 32; 53 uint32_t ht_control_field_bw20 : 32; 54 uint32_t ht_control_field_bw40 : 32; 55 uint32_t ht_control_field_bw80 : 32; 56 uint32_t ht_control_field_bw160 : 32; 57 uint32_t ht_control_overwrite_mask : 32; 58 uint32_t cas_control_info : 8, 59 cas_offset : 5, 60 cas_insertion_enable : 1, 61 reserved_10a : 2, 62 ht_control_overwrite_source_for_srp : 4, 63 ht_control_overwrite_source_for_bsrp : 4, 64 reserved_10b : 6, 65 mpdu_hdr_len_override_en : 1, 66 bar_ssn_overwrite_enable : 1; 67 uint32_t bar_ssn_offset : 12, 68 mpdu_hdr_len_override_val : 9, 69 reserved_11a : 11; 70 uint32_t ht_control_field_bw320 : 32; 71 uint32_t fw2sw_info : 32; 72 #else 73 uint32_t qos_ctl : 16, 74 frame_ctl : 16; 75 uint32_t reserved_1b : 6, 76 ht_control_overwrite_source : 4, 77 ht_control_overwrite_enable : 1, 78 buf_state_source : 1, 79 buf_state_sta_id : 1, 80 qos_buf_state_overwrite : 1, 81 key_id : 8, 82 checksum_tso_disable_for_frag : 1, 83 reserved_1a : 7, 84 tx_notify_no_htc_override : 1, 85 ampdu_flag : 1; 86 uint32_t base_pn_63_48 : 16, 87 bqr_rsvd_9_8 : 2, 88 ul_headroom_rsvd_7_6 : 2, 89 bqrp_offset : 5, 90 bqrp_insertion_enable : 1, 91 ul_headroom_offset : 5, 92 ul_headroom_insertion_enable : 1; 93 uint32_t base_pn_95_64 : 32; 94 uint32_t base_pn_127_96 : 32; 95 uint32_t ht_control_field_bw20 : 32; 96 uint32_t ht_control_field_bw40 : 32; 97 uint32_t ht_control_field_bw80 : 32; 98 uint32_t ht_control_field_bw160 : 32; 99 uint32_t ht_control_overwrite_mask : 32; 100 uint32_t bar_ssn_overwrite_enable : 1, 101 mpdu_hdr_len_override_en : 1, 102 reserved_10b : 6, 103 ht_control_overwrite_source_for_bsrp : 4, 104 ht_control_overwrite_source_for_srp : 4, 105 reserved_10a : 2, 106 cas_insertion_enable : 1, 107 cas_offset : 5, 108 cas_control_info : 8; 109 uint32_t reserved_11a : 11, 110 mpdu_hdr_len_override_val : 9, 111 bar_ssn_offset : 12; 112 uint32_t ht_control_field_bw320 : 32; 113 uint32_t fw2sw_info : 32; 114 #endif 115 }; 116 117 118 119 120 #define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 121 #define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 122 #define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 123 #define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff 124 125 126 127 128 #define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 129 #define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 130 #define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 131 #define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 132 133 134 135 136 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 137 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 138 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 139 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 140 141 142 143 144 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 145 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 146 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 147 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 148 149 150 151 152 #define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 153 #define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 154 #define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 155 #define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 156 157 158 159 160 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 161 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 162 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 163 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 164 165 166 167 168 #define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 169 #define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 170 #define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 171 #define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 172 173 174 175 176 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 177 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 178 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 179 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 180 181 182 183 184 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 185 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 186 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 187 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 188 189 190 191 192 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 193 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 194 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 195 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 196 197 198 199 200 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 201 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 202 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 203 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 204 205 206 207 208 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 209 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 210 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 211 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 212 213 214 215 216 #define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 217 #define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 218 #define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 219 #define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 220 221 222 223 224 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 225 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 226 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 227 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 228 229 230 231 232 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 233 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 234 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 235 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e 236 237 238 239 240 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 241 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 242 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 243 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 244 245 246 247 248 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 249 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 250 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 251 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 252 253 254 255 256 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 257 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 258 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 259 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 260 261 262 263 264 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 265 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 266 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 267 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 268 269 270 271 272 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 273 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 274 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 275 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 276 277 278 279 280 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 281 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 282 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 283 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 284 285 286 287 288 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 289 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 290 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 291 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff 292 293 294 295 296 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 297 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 298 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 299 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 300 301 302 303 304 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 305 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 306 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 307 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff 308 309 310 311 312 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 313 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 314 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 315 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 316 317 318 319 320 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 321 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 322 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 323 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff 324 325 326 327 328 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 329 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 330 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 331 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 332 333 334 335 336 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 337 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 338 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 339 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff 340 341 342 343 344 #define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 345 #define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 346 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 347 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 348 349 350 351 352 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 353 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 354 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 355 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 356 357 358 359 360 #define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 361 #define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 362 #define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 363 #define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 364 365 366 367 368 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 369 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 370 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 371 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 372 373 374 375 376 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 377 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 378 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 379 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 380 381 382 383 384 #define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 385 #define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 386 #define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 387 #define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003f000000 388 389 390 391 392 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 393 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 394 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 395 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 396 397 398 399 400 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 401 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 402 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 403 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 404 405 406 407 408 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 409 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 410 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 411 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 412 413 414 415 416 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 417 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 418 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 419 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 420 421 422 423 424 #define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 425 #define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 426 #define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 427 #define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 428 429 430 431 432 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 433 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 434 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 435 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff 436 437 438 439 440 #define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 441 #define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 442 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 443 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 444 445 446 447 #endif 448