1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TXPCU_BUFFER_STATUS_H_ 20 #define _TXPCU_BUFFER_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "txpcu_buffer_basics.h" 25 #define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 26 27 #define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 28 29 30 struct txpcu_buffer_status { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct txpcu_buffer_basics txpcu_basix_buffer_info; 33 uint32_t reserved : 15, 34 msdu_end : 1, 35 tx_data_sync_value : 16; 36 #else 37 struct txpcu_buffer_basics txpcu_basix_buffer_info; 38 uint32_t tx_data_sync_value : 16, 39 msdu_end : 1, 40 reserved : 15; 41 #endif 42 }; 43 44 45 46 47 48 49 50 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 51 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 52 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 53 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff 54 55 56 57 58 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 59 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 60 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 61 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 62 63 64 65 66 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 67 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 68 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 69 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 70 71 72 73 74 #define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 75 #define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 76 #define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 77 #define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 78 79 80 81 82 #define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 83 #define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 84 #define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 85 #define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 86 87 88 89 90 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 91 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 92 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 93 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 94 95 96 97 #endif 98