1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _U_SIG_EHT_TB_INFO_H_ 20 #define _U_SIG_EHT_TB_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 25 26 27 struct u_sig_eht_tb_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t phy_version : 3, 30 transmit_bw : 3, 31 dl_ul_flag : 1, 32 bss_color_id : 6, 33 txop_duration : 7, 34 disregard_0a : 6, 35 reserved_0c : 6; 36 uint32_t eht_ppdu_sig_cmn_type : 2, 37 validate_1a : 1, 38 spatial_reuse : 8, 39 disregard_1b : 5, 40 crc : 4, 41 tail : 6, 42 reserved_1c : 5, 43 rx_integrity_check_passed : 1; 44 #else 45 uint32_t reserved_0c : 6, 46 disregard_0a : 6, 47 txop_duration : 7, 48 bss_color_id : 6, 49 dl_ul_flag : 1, 50 transmit_bw : 3, 51 phy_version : 3; 52 uint32_t rx_integrity_check_passed : 1, 53 reserved_1c : 5, 54 tail : 6, 55 crc : 4, 56 disregard_1b : 5, 57 spatial_reuse : 8, 58 validate_1a : 1, 59 eht_ppdu_sig_cmn_type : 2; 60 #endif 61 }; 62 63 64 65 66 #define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 67 #define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 68 #define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 69 #define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 70 71 72 73 74 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 75 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 76 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 77 #define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 78 79 80 81 82 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 83 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 84 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 85 #define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 86 87 88 89 90 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 91 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 92 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 93 #define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 94 95 96 97 98 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 99 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 100 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 101 #define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 102 103 104 105 106 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 107 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 108 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 109 #define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 110 111 112 113 114 #define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 115 #define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 116 #define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 117 #define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 118 119 120 121 122 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 123 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 124 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 125 #define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 126 127 128 129 130 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 131 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 132 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 133 #define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 134 135 136 137 138 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 139 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 140 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 141 #define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 142 143 144 145 146 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 147 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 148 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 149 #define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 150 151 152 153 154 #define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 155 #define U_SIG_EHT_TB_INFO_CRC_LSB 16 156 #define U_SIG_EHT_TB_INFO_CRC_MSB 19 157 #define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 158 159 160 161 162 #define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 163 #define U_SIG_EHT_TB_INFO_TAIL_LSB 20 164 #define U_SIG_EHT_TB_INFO_TAIL_MSB 25 165 #define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 166 167 168 169 170 #define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 171 #define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 172 #define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 173 #define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 174 175 176 177 178 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 179 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 180 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 181 #define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 182 183 184 185 #endif 186