1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _WBM2SW_COMPLETION_RING_TX_H_ 20 #define _WBM2SW_COMPLETION_RING_TX_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "tx_rate_stats_info.h" 25 #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 26 27 28 struct wbm2sw_completion_ring_tx { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 uint32_t buffer_virt_addr_31_0 : 32; 31 uint32_t buffer_virt_addr_63_32 : 32; 32 uint32_t release_source_module : 3, 33 cache_id : 1, 34 reserved_2a : 2, 35 buffer_or_desc_type : 3, 36 return_buffer_manager : 4, 37 tqm_release_reason : 4, 38 rbm_override_valid : 1, 39 sw_buffer_cookie_11_0 : 12, 40 cookie_conversion_status : 1, 41 wbm_internal_error : 1; 42 uint32_t tqm_status_number : 24, 43 transmit_count : 7, 44 sw_release_details_valid : 1; 45 uint32_t ack_frame_rssi : 8, 46 first_msdu : 1, 47 last_msdu : 1, 48 fw_tx_notify_frame : 3, 49 buffer_timestamp : 19; 50 struct tx_rate_stats_info tx_rate_stats; 51 uint32_t sw_peer_id : 16, 52 tid : 4, 53 sw_buffer_cookie_19_12 : 8, 54 looping_count : 4; 55 #else 56 uint32_t buffer_virt_addr_31_0 : 32; 57 uint32_t buffer_virt_addr_63_32 : 32; 58 uint32_t wbm_internal_error : 1, 59 cookie_conversion_status : 1, 60 sw_buffer_cookie_11_0 : 12, 61 rbm_override_valid : 1, 62 tqm_release_reason : 4, 63 return_buffer_manager : 4, 64 buffer_or_desc_type : 3, 65 reserved_2a : 2, 66 cache_id : 1, 67 release_source_module : 3; 68 uint32_t sw_release_details_valid : 1, 69 transmit_count : 7, 70 tqm_status_number : 24; 71 uint32_t buffer_timestamp : 19, 72 fw_tx_notify_frame : 3, 73 last_msdu : 1, 74 first_msdu : 1, 75 ack_frame_rssi : 8; 76 struct tx_rate_stats_info tx_rate_stats; 77 uint32_t looping_count : 4, 78 sw_buffer_cookie_19_12 : 8, 79 tid : 4, 80 sw_peer_id : 16; 81 #endif 82 }; 83 84 85 86 87 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 88 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 89 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 90 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 91 92 93 94 95 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 96 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 97 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 98 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 99 100 101 102 103 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 104 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 105 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 106 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 107 108 109 110 111 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 112 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 113 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 114 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 115 116 117 118 119 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 120 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 121 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 122 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 123 124 125 126 127 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 128 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 129 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 130 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 131 132 133 134 135 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 136 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 137 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 138 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 139 140 141 142 143 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 144 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 145 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 146 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 147 148 149 150 151 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 152 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 153 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 154 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 155 156 157 158 159 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 160 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 161 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 162 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 163 164 165 166 167 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 168 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 169 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 170 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 171 172 173 174 175 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 176 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 177 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 178 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 179 180 181 182 183 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c 184 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 185 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 186 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff 187 188 189 190 191 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c 192 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 193 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 194 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 195 196 197 198 199 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c 200 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 201 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 202 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 203 204 205 206 207 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 208 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 209 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 210 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff 211 212 213 214 215 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 216 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 217 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 218 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 219 220 221 222 223 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 224 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 225 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 226 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 227 228 229 230 231 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 232 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 233 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 234 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 235 236 237 238 239 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 240 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 241 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 242 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 243 244 245 246 247 248 249 250 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 251 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 252 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 253 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 254 255 256 257 258 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 259 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 260 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 261 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e 262 263 264 265 266 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 267 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 268 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 269 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 270 271 272 273 274 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 275 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 276 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 277 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 278 279 280 281 282 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 283 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 284 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 285 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 286 287 288 289 290 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 291 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 292 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 293 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 294 295 296 297 298 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 299 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 300 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 301 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 302 303 304 305 306 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 307 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 308 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 309 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 310 311 312 313 314 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 315 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 316 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 317 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 318 319 320 321 322 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 323 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 324 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 325 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 326 327 328 329 330 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 331 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 332 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 333 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff 334 335 336 337 338 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c 339 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 340 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 341 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff 342 343 344 345 346 #define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c 347 #define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 348 #define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 349 #define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 350 351 352 353 354 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c 355 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 356 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 357 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 358 359 360 361 362 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c 363 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 364 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 365 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 366 367 368 369 #endif 370