1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _WBM_RELEASE_RING_H_ 20 #define _WBM_RELEASE_RING_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "buffer_addr_info.h" 25 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 26 27 28 struct wbm_release_ring { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct buffer_addr_info released_buff_or_desc_addr_info; 31 uint32_t release_source_module : 3, 32 reserved_2a : 3, 33 buffer_or_desc_type : 3, 34 reserved_2b : 22, 35 wbm_internal_error : 1; 36 uint32_t reserved_3a : 32; 37 uint32_t reserved_4a : 32; 38 uint32_t reserved_5a : 32; 39 uint32_t reserved_6a : 32; 40 uint32_t reserved_7a : 28, 41 looping_count : 4; 42 #else 43 struct buffer_addr_info released_buff_or_desc_addr_info; 44 uint32_t wbm_internal_error : 1, 45 reserved_2b : 22, 46 buffer_or_desc_type : 3, 47 reserved_2a : 3, 48 release_source_module : 3; 49 uint32_t reserved_3a : 32; 50 uint32_t reserved_4a : 32; 51 uint32_t reserved_5a : 32; 52 uint32_t reserved_6a : 32; 53 uint32_t looping_count : 4, 54 reserved_7a : 28; 55 #endif 56 }; 57 58 59 60 61 62 63 64 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 65 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 66 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 67 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 68 69 70 71 72 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 73 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 74 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 75 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 76 77 78 79 80 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 81 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 82 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 83 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 84 85 86 87 88 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 89 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 90 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 91 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 92 93 94 95 96 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 97 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 98 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 99 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 100 101 102 103 104 #define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 105 #define WBM_RELEASE_RING_RESERVED_2A_LSB 3 106 #define WBM_RELEASE_RING_RESERVED_2A_MSB 5 107 #define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 108 109 110 111 112 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 113 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 114 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 115 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 116 117 118 119 120 #define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 121 #define WBM_RELEASE_RING_RESERVED_2B_LSB 9 122 #define WBM_RELEASE_RING_RESERVED_2B_MSB 30 123 #define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 124 125 126 127 128 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 129 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 130 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 131 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 132 133 134 135 136 #define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c 137 #define WBM_RELEASE_RING_RESERVED_3A_LSB 0 138 #define WBM_RELEASE_RING_RESERVED_3A_MSB 31 139 #define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff 140 141 142 143 144 #define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 145 #define WBM_RELEASE_RING_RESERVED_4A_LSB 0 146 #define WBM_RELEASE_RING_RESERVED_4A_MSB 31 147 #define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff 148 149 150 151 152 #define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 153 #define WBM_RELEASE_RING_RESERVED_5A_LSB 0 154 #define WBM_RELEASE_RING_RESERVED_5A_MSB 31 155 #define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff 156 157 158 159 160 #define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 161 #define WBM_RELEASE_RING_RESERVED_6A_LSB 0 162 #define WBM_RELEASE_RING_RESERVED_6A_MSB 31 163 #define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff 164 165 166 167 168 #define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c 169 #define WBM_RELEASE_RING_RESERVED_7A_LSB 0 170 #define WBM_RELEASE_RING_RESERVED_7A_MSB 27 171 #define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff 172 173 174 175 176 #define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c 177 #define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 178 #define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 179 #define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 180 181 182 183 #endif 184