xref: /wlan-driver/fw-api/hw/qca5424/wbm_release_ring_rx.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /*
3  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4  * SPDX-License-Identifier: ISC
5  */
6 
7 
8 
9 
10 
11 
12 
13 
14 
15 
16 
17 
18 
19 #ifndef _WBM_RELEASE_RING_RX_H_
20 #define _WBM_RELEASE_RING_RX_H_
21 #if !defined(__ASSEMBLER__)
22 #endif
23 
24 #include "rx_msdu_desc_info.h"
25 #include "rx_mpdu_desc_info.h"
26 #include "buffer_addr_info.h"
27 #define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8
28 
29 
30 struct wbm_release_ring_rx {
31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
32              struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
33              uint32_t release_source_module                                   :  3,
34                       bm_action                                               :  3,
35                       buffer_or_desc_type                                     :  3,
36                       first_msdu_index                                        :  4,
37                       reserved_2a                                             :  2,
38                       cache_id                                                :  1,
39                       cookie_conversion_status                                :  1,
40                       rxdma_push_reason                                       :  2,
41                       rxdma_error_code                                        :  5,
42                       reo_push_reason                                         :  2,
43                       reo_error_code                                          :  5,
44                       wbm_internal_error                                      :  1;
45              struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
46              struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
47              uint32_t reserved_6a                                             : 32;
48              uint32_t reserved_7a                                             : 20,
49                       ring_id                                                 :  8,
50                       looping_count                                           :  4;
51 #else
52              struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
53              uint32_t wbm_internal_error                                      :  1,
54                       reo_error_code                                          :  5,
55                       reo_push_reason                                         :  2,
56                       rxdma_error_code                                        :  5,
57                       rxdma_push_reason                                       :  2,
58                       cookie_conversion_status                                :  1,
59                       cache_id                                                :  1,
60                       reserved_2a                                             :  2,
61                       first_msdu_index                                        :  4,
62                       buffer_or_desc_type                                     :  3,
63                       bm_action                                               :  3,
64                       release_source_module                                   :  3;
65              struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
66              struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
67              uint32_t reserved_6a                                             : 32;
68              uint32_t looping_count                                           :  4,
69                       ring_id                                                 :  8,
70                       reserved_7a                                             : 20;
71 #endif
72 };
73 
74 
75 
76 
77 
78 
79 
80 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
81 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
82 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
83 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
84 
85 
86 
87 
88 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
89 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
90 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
91 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
92 
93 
94 
95 
96 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
97 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
98 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
99 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
100 
101 
102 
103 
104 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
105 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
106 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
107 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
108 
109 
110 
111 
112 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
113 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB                               0
114 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB                               2
115 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
116 
117 
118 
119 
120 #define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET                                        0x00000008
121 #define WBM_RELEASE_RING_RX_BM_ACTION_LSB                                           3
122 #define WBM_RELEASE_RING_RX_BM_ACTION_MSB                                           5
123 #define WBM_RELEASE_RING_RX_BM_ACTION_MASK                                          0x00000038
124 
125 
126 
127 
128 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
129 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB                                 6
130 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB                                 8
131 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK                                0x000001c0
132 
133 
134 
135 
136 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET                                 0x00000008
137 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB                                    9
138 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB                                    12
139 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK                                   0x00001e00
140 
141 
142 
143 
144 #define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET                                      0x00000008
145 #define WBM_RELEASE_RING_RX_RESERVED_2A_LSB                                         13
146 #define WBM_RELEASE_RING_RX_RESERVED_2A_MSB                                         14
147 #define WBM_RELEASE_RING_RX_RESERVED_2A_MASK                                        0x00006000
148 
149 
150 
151 
152 #define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET                                         0x00000008
153 #define WBM_RELEASE_RING_RX_CACHE_ID_LSB                                            15
154 #define WBM_RELEASE_RING_RX_CACHE_ID_MSB                                            15
155 #define WBM_RELEASE_RING_RX_CACHE_ID_MASK                                           0x00008000
156 
157 
158 
159 
160 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET                         0x00000008
161 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB                            16
162 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB                            16
163 #define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK                           0x00010000
164 
165 
166 
167 
168 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET                                0x00000008
169 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB                                   17
170 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB                                   18
171 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK                                  0x00060000
172 
173 
174 
175 
176 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET                                 0x00000008
177 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB                                    19
178 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB                                    23
179 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK                                   0x00f80000
180 
181 
182 
183 
184 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET                                  0x00000008
185 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB                                     24
186 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB                                     25
187 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK                                    0x03000000
188 
189 
190 
191 
192 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET                                   0x00000008
193 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB                                      26
194 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB                                      30
195 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK                                     0x7c000000
196 
197 
198 
199 
200 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET                               0x00000008
201 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB                                  31
202 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB                                  31
203 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK                                 0x80000000
204 
205 
206 
207 
208 
209 
210 
211 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET             0x0000000c
212 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB                0
213 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB                7
214 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK               0x000000ff
215 
216 
217 
218 
219 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET          0x0000000c
220 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB             8
221 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB             8
222 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK            0x00000100
223 
224 
225 
226 
227 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET         0x0000000c
228 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB            9
229 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB            9
230 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK           0x00000200
231 
232 
233 
234 
235 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET             0x0000000c
236 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB                10
237 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB                10
238 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK               0x00000400
239 
240 
241 
242 
243 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET              0x0000000c
244 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB                 11
245 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB                 11
246 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK                0x00000800
247 
248 
249 
250 
251 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c
252 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
253 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
254 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
255 
256 
257 
258 
259 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET               0x0000000c
260 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB                  13
261 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB                  13
262 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK                 0x00002000
263 
264 
265 
266 
267 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET     0x0000000c
268 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB        14
269 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB        14
270 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK       0x00004000
271 
272 
273 
274 
275 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET               0x0000000c
276 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB                  15
277 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB                  26
278 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK                 0x07ff8000
279 
280 
281 
282 
283 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c
284 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB    27
285 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB    27
286 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK   0x08000000
287 
288 
289 
290 
291 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET                    0x0000000c
292 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                       28
293 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                       31
294 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                      0xf0000000
295 
296 
297 
298 
299 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET         0x00000010
300 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB            0
301 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB            31
302 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK           0xffffffff
303 
304 
305 
306 
307 
308 
309 
310 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
311 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
312 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
313 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
314 
315 
316 
317 
318 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
319 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
320 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
321 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
322 
323 
324 
325 
326 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000014
327 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
328 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
329 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
330 
331 
332 
333 
334 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000014
335 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
336 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
337 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
338 
339 
340 
341 
342 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000014
343 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
344 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
345 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
346 
347 
348 
349 
350 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000014
351 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
352 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
353 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
354 
355 
356 
357 
358 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000014
359 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
360 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
361 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
362 
363 
364 
365 
366 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000014
367 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
368 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
369 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
370 
371 
372 
373 
374 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000014
375 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
376 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
377 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
378 
379 
380 
381 
382 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000014
383 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
384 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
385 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
386 
387 
388 
389 
390 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000014
391 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
392 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
393 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
394 
395 
396 
397 
398 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000014
399 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
400 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
401 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
402 
403 
404 
405 
406 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000014
407 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
408 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
409 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
410 
411 
412 
413 
414 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000014
415 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
416 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
417 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
418 
419 
420 
421 
422 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000014
423 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
424 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
425 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
426 
427 
428 
429 
430 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000014
431 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
432 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
433 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
434 
435 
436 
437 
438 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET      0x00000014
439 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB         31
440 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB         31
441 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK        0x80000000
442 
443 
444 
445 
446 #define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET                                      0x00000018
447 #define WBM_RELEASE_RING_RX_RESERVED_6A_LSB                                         0
448 #define WBM_RELEASE_RING_RX_RESERVED_6A_MSB                                         31
449 #define WBM_RELEASE_RING_RX_RESERVED_6A_MASK                                        0xffffffff
450 
451 
452 
453 
454 #define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET                                      0x0000001c
455 #define WBM_RELEASE_RING_RX_RESERVED_7A_LSB                                         0
456 #define WBM_RELEASE_RING_RX_RESERVED_7A_MSB                                         19
457 #define WBM_RELEASE_RING_RX_RESERVED_7A_MASK                                        0x000fffff
458 
459 
460 
461 
462 #define WBM_RELEASE_RING_RX_RING_ID_OFFSET                                          0x0000001c
463 #define WBM_RELEASE_RING_RX_RING_ID_LSB                                             20
464 #define WBM_RELEASE_RING_RX_RING_ID_MSB                                             27
465 #define WBM_RELEASE_RING_RX_RING_ID_MASK                                            0x0ff00000
466 
467 
468 
469 
470 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET                                    0x0000001c
471 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB                                       28
472 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB                                       31
473 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK                                      0xf0000000
474 
475 
476 
477 #endif
478