1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 20 #define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_reo_status_header.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0-1 struct uniform_reo_status_header status_header; 30 // 2 threshold_index[1:0], reserved_2[31:2] 31 // 3 link_descriptor_counter0[23:0], reserved_3[31:24] 32 // 4 link_descriptor_counter1[23:0], reserved_4[31:24] 33 // 5 link_descriptor_counter2[23:0], reserved_5[31:24] 34 // 6 link_descriptor_counter_sum[25:0], reserved_6[31:26] 35 // 7 reserved_7[31:0] 36 // 8 reserved_8[31:0] 37 // 9 reserved_9a[31:0] 38 // 10 reserved_10a[31:0] 39 // 11 reserved_11a[31:0] 40 // 12 reserved_12a[31:0] 41 // 13 reserved_13a[31:0] 42 // 14 reserved_14a[31:0] 43 // 15 reserved_15a[31:0] 44 // 16 reserved_16a[31:0] 45 // 17 reserved_17a[31:0] 46 // 18 reserved_18a[31:0] 47 // 19 reserved_19a[31:0] 48 // 20 reserved_20a[31:0] 49 // 21 reserved_21a[31:0] 50 // 22 reserved_22a[31:0] 51 // 23 reserved_23a[31:0] 52 // 24 reserved_24a[27:0], looping_count[31:28] 53 // 54 // ################ END SUMMARY ################# 55 56 #define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25 57 58 struct reo_descriptor_threshold_reached_status { 59 struct uniform_reo_status_header status_header; 60 uint32_t threshold_index : 2, //[1:0] 61 reserved_2 : 30; //[31:2] 62 uint32_t link_descriptor_counter0 : 24, //[23:0] 63 reserved_3 : 8; //[31:24] 64 uint32_t link_descriptor_counter1 : 24, //[23:0] 65 reserved_4 : 8; //[31:24] 66 uint32_t link_descriptor_counter2 : 24, //[23:0] 67 reserved_5 : 8; //[31:24] 68 uint32_t link_descriptor_counter_sum : 26, //[25:0] 69 reserved_6 : 6; //[31:26] 70 uint32_t reserved_7 : 32; //[31:0] 71 uint32_t reserved_8 : 32; //[31:0] 72 uint32_t reserved_9a : 32; //[31:0] 73 uint32_t reserved_10a : 32; //[31:0] 74 uint32_t reserved_11a : 32; //[31:0] 75 uint32_t reserved_12a : 32; //[31:0] 76 uint32_t reserved_13a : 32; //[31:0] 77 uint32_t reserved_14a : 32; //[31:0] 78 uint32_t reserved_15a : 32; //[31:0] 79 uint32_t reserved_16a : 32; //[31:0] 80 uint32_t reserved_17a : 32; //[31:0] 81 uint32_t reserved_18a : 32; //[31:0] 82 uint32_t reserved_19a : 32; //[31:0] 83 uint32_t reserved_20a : 32; //[31:0] 84 uint32_t reserved_21a : 32; //[31:0] 85 uint32_t reserved_22a : 32; //[31:0] 86 uint32_t reserved_23a : 32; //[31:0] 87 uint32_t reserved_24a : 28, //[27:0] 88 looping_count : 4; //[31:28] 89 }; 90 91 /* 92 93 struct uniform_reo_status_header status_header 94 95 Consumer: SW 96 97 Producer: REO 98 99 100 101 Details that can link this status with the original 102 command. It also contains info on how long REO took to 103 execute this command. 104 105 threshold_index 106 107 The index of the threshold register whose value got 108 reached 109 110 111 112 <enum 0 reo_desc_counter0_threshold> 113 114 <enum 1 reo_desc_counter1_threshold> 115 116 <enum 2 reo_desc_counter2_threshold> 117 118 <enum 3 reo_desc_counter_sum_threshold> 119 120 121 122 <legal all> 123 124 reserved_2 125 126 <legal 0> 127 128 link_descriptor_counter0 129 130 Value of this counter at generation of this message 131 132 <legal all> 133 134 reserved_3 135 136 <legal 0> 137 138 link_descriptor_counter1 139 140 Value of this counter at generation of this message 141 142 <legal all> 143 144 reserved_4 145 146 <legal 0> 147 148 link_descriptor_counter2 149 150 Value of this counter at generation of this message 151 152 <legal all> 153 154 reserved_5 155 156 <legal 0> 157 158 link_descriptor_counter_sum 159 160 Value of this counter at generation of this message 161 162 <legal all> 163 164 reserved_6 165 166 <legal 0> 167 168 reserved_7 169 170 <legal 0> 171 172 reserved_8 173 174 <legal 0> 175 176 reserved_9a 177 178 <legal 0> 179 180 reserved_10a 181 182 <legal 0> 183 184 reserved_11a 185 186 <legal 0> 187 188 reserved_12a 189 190 <legal 0> 191 192 reserved_13a 193 194 <legal 0> 195 196 reserved_14a 197 198 <legal 0> 199 200 reserved_15a 201 202 <legal 0> 203 204 reserved_16a 205 206 <legal 0> 207 208 reserved_17a 209 210 <legal 0> 211 212 reserved_18a 213 214 <legal 0> 215 216 reserved_19a 217 218 <legal 0> 219 220 reserved_20a 221 222 <legal 0> 223 224 reserved_21a 225 226 <legal 0> 227 228 reserved_22a 229 230 <legal 0> 231 232 reserved_23a 233 234 <legal 0> 235 236 reserved_24a 237 238 <legal 0> 239 240 looping_count 241 242 A count value that indicates the number of times the 243 producer of entries into this Ring has looped around the 244 ring. 245 246 At initialization time, this value is set to 0. On the 247 first loop, this value is set to 1. After the max value is 248 reached allowed by the number of bits for this field, the 249 count value continues with 0 again. 250 251 252 253 In case SW is the consumer of the ring entries, it can 254 use this field to figure out up to where the producer of 255 entries has created new entries. This eliminates the need to 256 check where the head pointer' of the ring is located once 257 the SW starts processing an interrupt indicating that new 258 entries have been put into this ring... 259 260 261 262 Also note that SW if it wants only needs to look at the 263 LSB bit of this count value. 264 265 <legal all> 266 */ 267 268 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000 269 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 270 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff 271 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004 272 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28 273 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff 274 275 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX 276 277 The index of the threshold register whose value got 278 reached 279 280 281 282 <enum 0 reo_desc_counter0_threshold> 283 284 <enum 1 reo_desc_counter1_threshold> 285 286 <enum 2 reo_desc_counter2_threshold> 287 288 <enum 3 reo_desc_counter_sum_threshold> 289 290 291 292 <legal all> 293 */ 294 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008 295 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0 296 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003 297 298 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2 299 300 <legal 0> 301 */ 302 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008 303 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2 304 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc 305 306 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0 307 308 Value of this counter at generation of this message 309 310 <legal all> 311 */ 312 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c 313 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0 314 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff 315 316 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3 317 318 <legal 0> 319 */ 320 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c 321 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24 322 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000 323 324 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1 325 326 Value of this counter at generation of this message 327 328 <legal all> 329 */ 330 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010 331 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0 332 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff 333 334 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4 335 336 <legal 0> 337 */ 338 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010 339 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24 340 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000 341 342 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2 343 344 Value of this counter at generation of this message 345 346 <legal all> 347 */ 348 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014 349 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0 350 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff 351 352 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5 353 354 <legal 0> 355 */ 356 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014 357 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24 358 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000 359 360 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM 361 362 Value of this counter at generation of this message 363 364 <legal all> 365 */ 366 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018 367 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 368 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff 369 370 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6 371 372 <legal 0> 373 */ 374 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018 375 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26 376 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000 377 378 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7 379 380 <legal 0> 381 */ 382 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c 383 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0 384 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff 385 386 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8 387 388 <legal 0> 389 */ 390 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020 391 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0 392 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff 393 394 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A 395 396 <legal 0> 397 */ 398 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024 399 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0 400 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff 401 402 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A 403 404 <legal 0> 405 */ 406 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028 407 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0 408 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff 409 410 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A 411 412 <legal 0> 413 */ 414 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c 415 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0 416 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff 417 418 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A 419 420 <legal 0> 421 */ 422 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030 423 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0 424 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff 425 426 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A 427 428 <legal 0> 429 */ 430 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034 431 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0 432 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff 433 434 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A 435 436 <legal 0> 437 */ 438 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038 439 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0 440 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff 441 442 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A 443 444 <legal 0> 445 */ 446 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c 447 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0 448 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff 449 450 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A 451 452 <legal 0> 453 */ 454 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040 455 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0 456 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff 457 458 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A 459 460 <legal 0> 461 */ 462 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044 463 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0 464 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff 465 466 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A 467 468 <legal 0> 469 */ 470 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048 471 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0 472 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff 473 474 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A 475 476 <legal 0> 477 */ 478 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c 479 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0 480 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff 481 482 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A 483 484 <legal 0> 485 */ 486 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050 487 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0 488 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff 489 490 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A 491 492 <legal 0> 493 */ 494 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054 495 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0 496 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff 497 498 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A 499 500 <legal 0> 501 */ 502 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058 503 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0 504 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff 505 506 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A 507 508 <legal 0> 509 */ 510 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c 511 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0 512 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff 513 514 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A 515 516 <legal 0> 517 */ 518 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060 519 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0 520 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff 521 522 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT 523 524 A count value that indicates the number of times the 525 producer of entries into this Ring has looped around the 526 ring. 527 528 At initialization time, this value is set to 0. On the 529 first loop, this value is set to 1. After the max value is 530 reached allowed by the number of bits for this field, the 531 count value continues with 0 again. 532 533 534 535 In case SW is the consumer of the ring entries, it can 536 use this field to figure out up to where the producer of 537 entries has created new entries. This eliminates the need to 538 check where the head pointer' of the ring is located once 539 the SW starts processing an interrupt indicating that new 540 entries have been put into this ring... 541 542 543 544 Also note that SW if it wants only needs to look at the 545 LSB bit of this count value. 546 547 <legal all> 548 */ 549 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 550 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28 551 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 552 553 554 #endif // _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 555