1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _REO_ENTRANCE_RING_H_ 20 #define _REO_ENTRANCE_RING_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "rx_mpdu_details.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; 30 // 4 rx_reo_queue_desc_addr_31_0[31:0] 31 // 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28] 32 // 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], reserved_6a[31:7] 33 // 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] 34 // 35 // ################ END SUMMARY ################# 36 37 #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 38 39 struct reo_entrance_ring { 40 struct rx_mpdu_details reo_level_mpdu_frame_info; 41 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 42 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 43 rounded_mpdu_byte_count : 14, //[21:8] 44 reo_destination_indication : 5, //[26:22] 45 frameless_bar : 1, //[27] 46 reserved_5a : 4; //[31:28] 47 uint32_t rxdma_push_reason : 2, //[1:0] 48 rxdma_error_code : 5, //[6:2] 49 reserved_6a : 25; //[31:7] 50 uint32_t reserved_7a : 20, //[19:0] 51 ring_id : 8, //[27:20] 52 looping_count : 4; //[31:28] 53 }; 54 55 /* 56 57 struct rx_mpdu_details reo_level_mpdu_frame_info 58 59 Consumer: REO 60 61 Producer: RXDMA 62 63 64 65 Details related to the MPDU being pushed into the REO 66 67 rx_reo_queue_desc_addr_31_0 68 69 Consumer: REO 70 71 Producer: RXDMA 72 73 74 75 Address (lower 32 bits) of the REO queue descriptor. 76 77 <legal all> 78 79 rx_reo_queue_desc_addr_39_32 80 81 Consumer: REO 82 83 Producer: RXDMA 84 85 86 87 Address (upper 8 bits) of the REO queue descriptor. 88 89 <legal all> 90 91 rounded_mpdu_byte_count 92 93 An approximation of the number of bytes received in this 94 MPDU. 95 96 Used to keeps stats on the amount of data flowing 97 through a queue. 98 99 <legal all> 100 101 reo_destination_indication 102 103 RXDMA copy the MPDU's first MSDU's destination 104 indication field here. This is used for REO to be able to 105 re-route the packet to a different SW destination ring if 106 the packet is detected as error in REO. 107 108 109 110 The ID of the REO exit ring where the MSDU frame shall 111 push after (MPDU level) reordering has finished. 112 113 114 115 <enum 0 reo_destination_tcl> Reo will push the frame 116 into the REO2TCL ring 117 118 <enum 1 reo_destination_sw1> Reo will push the frame 119 into the REO2SW1 ring 120 121 <enum 2 reo_destination_sw2> Reo will push the frame 122 into the REO2SW1 ring 123 124 <enum 3 reo_destination_sw3> Reo will push the frame 125 into the REO2SW1 ring 126 127 <enum 4 reo_destination_sw4> Reo will push the frame 128 into the REO2SW1 ring 129 130 <enum 5 reo_destination_release> Reo will push the frame 131 into the REO_release ring 132 133 <enum 6 reo_destination_fw> Reo will push the frame into 134 the REO2FW ring 135 136 <enum 7 reo_destination_7> REO remaps this 137 138 <enum 8 reo_destination_8> REO remaps this <enum 9 139 reo_destination_9> REO remaps this <enum 10 140 reo_destination_10> REO remaps this 141 142 <enum 11 reo_destination_11> REO remaps this 143 144 <enum 12 reo_destination_12> REO remaps this <enum 13 145 reo_destination_13> REO remaps this 146 147 <enum 14 reo_destination_14> REO remaps this 148 149 <enum 15 reo_destination_15> REO remaps this 150 151 <enum 16 reo_destination_16> REO remaps this 152 153 <enum 17 reo_destination_17> REO remaps this 154 155 <enum 18 reo_destination_18> REO remaps this 156 157 <enum 19 reo_destination_19> REO remaps this 158 159 <enum 20 reo_destination_20> REO remaps this 160 161 <enum 21 reo_destination_21> REO remaps this 162 163 <enum 22 reo_destination_22> REO remaps this 164 165 <enum 23 reo_destination_23> REO remaps this 166 167 <enum 24 reo_destination_24> REO remaps this 168 169 <enum 25 reo_destination_25> REO remaps this 170 171 <enum 26 reo_destination_26> REO remaps this 172 173 <enum 27 reo_destination_27> REO remaps this 174 175 <enum 28 reo_destination_28> REO remaps this 176 177 <enum 29 reo_destination_29> REO remaps this 178 179 <enum 30 reo_destination_30> REO remaps this 180 181 <enum 31 reo_destination_31> REO remaps this 182 183 184 185 <legal all> 186 187 frameless_bar 188 189 When set, this REO entrance ring struct contains BAR 190 info from a multi TID BAR frame. The original multi TID BAR 191 frame itself contained all the REO info for the first TID, 192 but all the subsequent TID info and their linkage to the REO 193 descriptors is passed down as 'frameless' BAR info. 194 195 196 197 The only fields valid in this descriptor when this bit 198 is set are: 199 200 Rx_reo_queue_desc_addr_31_0 201 202 RX_reo_queue_desc_addr_39_32 203 204 205 206 And within the 207 208 Reo_level_mpdu_frame_info: 209 210 Within Rx_mpdu_desc_info_details: 211 212 Mpdu_Sequence_number 213 214 BAR_frame 215 216 Peer_meta_data 217 218 All other fields shall be set to 0 219 220 221 222 <legal all> 223 224 reserved_5a 225 226 <legal 0> 227 228 rxdma_push_reason 229 230 Indicates why rxdma pushed the frame to this ring 231 232 233 234 This field is ignored by REO. 235 236 237 238 <enum 0 rxdma_error_detected> RXDMA detected an error an 239 pushed this frame to this queue 240 241 <enum 1 rxdma_routing_instruction> RXDMA pushed the 242 frame to this queue per received routing instructions. No 243 error within RXDMA was detected 244 245 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 246 result the MSDU link descriptor might not have the 247 last_msdu_in_mpdu_flag set, but instead WBM might just see a 248 NULL pointer in the MSDU link descriptor. This is to be 249 considered a normal condition for this scenario. 250 251 252 253 <legal 0 - 2> 254 255 rxdma_error_code 256 257 Field only valid when 'rxdma_push_reason' set to 258 'rxdma_error_detected'. 259 260 261 262 This field is ignored by REO. 263 264 265 266 <enum 0 rxdma_overflow_err>MPDU frame is not complete 267 due to a FIFO overflow error in RXPCU. 268 269 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 270 due to receiving incomplete MPDU from the PHY 271 272 273 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 274 error or CRYPTO received an encrypted frame, but did not get 275 a valid corresponding key id in the peer entry. 276 277 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 278 error 279 280 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 281 unencrypted frame error when encrypted was expected 282 283 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 284 length error 285 286 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 287 number of MSDUs allowed in an MPDU got exceeded 288 289 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 290 error 291 292 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 293 parsing error 294 295 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 296 during SA search 297 298 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 299 during DA search 300 301 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 302 timeout during flow search 303 304 <enum 13 Rxdma_flush_request>RXDMA received a flush 305 request 306 307 reserved_6a 308 309 <legal 0> 310 311 reserved_7a 312 313 <legal 0> 314 315 ring_id 316 317 Consumer: SW/REO/DEBUG 318 319 Producer: SRNG (of RXDMA) 320 321 322 323 For debugging. 324 325 This field is filled in by the SRNG module. 326 327 It help to identify the ring that is being looked <legal 328 all> 329 330 looping_count 331 332 Consumer: SW/REO/DEBUG 333 334 Producer: SRNG (of RXDMA) 335 336 337 338 For debugging. 339 340 This field is filled in by the SRNG module. 341 342 343 344 A count value that indicates the number of times the 345 producer of entries into this Ring has looped around the 346 ring. 347 348 At initialization time, this value is set to 0. On the 349 first loop, this value is set to 1. After the max value is 350 reached allowed by the number of bits for this field, the 351 count value continues with 0 again. 352 353 354 355 In case SW is the consumer of the ring entries, it can 356 use this field to figure out up to where the producer of 357 entries has created new entries. This eliminates the need to 358 check where the head pointer' of the ring is located once 359 the SW starts processing an interrupt indicating that new 360 entries have been put into this ring... 361 362 363 364 Also note that SW if it wants only needs to look at the 365 LSB bit of this count value. 366 367 <legal all> 368 */ 369 370 #define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000000 371 #define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 372 #define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff 373 #define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000004 374 #define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 375 #define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff 376 #define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000008 377 #define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 378 #define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff 379 #define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x0000000c 380 #define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28 381 #define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff 382 383 /* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0 384 385 Consumer: REO 386 387 Producer: RXDMA 388 389 390 391 Address (lower 32 bits) of the REO queue descriptor. 392 393 <legal all> 394 */ 395 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 396 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 397 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 398 399 /* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32 400 401 Consumer: REO 402 403 Producer: RXDMA 404 405 406 407 Address (upper 8 bits) of the REO queue descriptor. 408 409 <legal all> 410 */ 411 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 412 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 413 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 414 415 /* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT 416 417 An approximation of the number of bytes received in this 418 MPDU. 419 420 Used to keeps stats on the amount of data flowing 421 through a queue. 422 423 <legal all> 424 */ 425 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 426 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 427 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 428 429 /* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION 430 431 RXDMA copy the MPDU's first MSDU's destination 432 indication field here. This is used for REO to be able to 433 re-route the packet to a different SW destination ring if 434 the packet is detected as error in REO. 435 436 437 438 The ID of the REO exit ring where the MSDU frame shall 439 push after (MPDU level) reordering has finished. 440 441 442 443 <enum 0 reo_destination_tcl> Reo will push the frame 444 into the REO2TCL ring 445 446 <enum 1 reo_destination_sw1> Reo will push the frame 447 into the REO2SW1 ring 448 449 <enum 2 reo_destination_sw2> Reo will push the frame 450 into the REO2SW1 ring 451 452 <enum 3 reo_destination_sw3> Reo will push the frame 453 into the REO2SW1 ring 454 455 <enum 4 reo_destination_sw4> Reo will push the frame 456 into the REO2SW1 ring 457 458 <enum 5 reo_destination_release> Reo will push the frame 459 into the REO_release ring 460 461 <enum 6 reo_destination_fw> Reo will push the frame into 462 the REO2FW ring 463 464 <enum 7 reo_destination_7> REO remaps this 465 466 <enum 8 reo_destination_8> REO remaps this <enum 9 467 reo_destination_9> REO remaps this <enum 10 468 reo_destination_10> REO remaps this 469 470 <enum 11 reo_destination_11> REO remaps this 471 472 <enum 12 reo_destination_12> REO remaps this <enum 13 473 reo_destination_13> REO remaps this 474 475 <enum 14 reo_destination_14> REO remaps this 476 477 <enum 15 reo_destination_15> REO remaps this 478 479 <enum 16 reo_destination_16> REO remaps this 480 481 <enum 17 reo_destination_17> REO remaps this 482 483 <enum 18 reo_destination_18> REO remaps this 484 485 <enum 19 reo_destination_19> REO remaps this 486 487 <enum 20 reo_destination_20> REO remaps this 488 489 <enum 21 reo_destination_21> REO remaps this 490 491 <enum 22 reo_destination_22> REO remaps this 492 493 <enum 23 reo_destination_23> REO remaps this 494 495 <enum 24 reo_destination_24> REO remaps this 496 497 <enum 25 reo_destination_25> REO remaps this 498 499 <enum 26 reo_destination_26> REO remaps this 500 501 <enum 27 reo_destination_27> REO remaps this 502 503 <enum 28 reo_destination_28> REO remaps this 504 505 <enum 29 reo_destination_29> REO remaps this 506 507 <enum 30 reo_destination_30> REO remaps this 508 509 <enum 31 reo_destination_31> REO remaps this 510 511 512 513 <legal all> 514 */ 515 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 516 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 517 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 518 519 /* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR 520 521 When set, this REO entrance ring struct contains BAR 522 info from a multi TID BAR frame. The original multi TID BAR 523 frame itself contained all the REO info for the first TID, 524 but all the subsequent TID info and their linkage to the REO 525 descriptors is passed down as 'frameless' BAR info. 526 527 528 529 The only fields valid in this descriptor when this bit 530 is set are: 531 532 Rx_reo_queue_desc_addr_31_0 533 534 RX_reo_queue_desc_addr_39_32 535 536 537 538 And within the 539 540 Reo_level_mpdu_frame_info: 541 542 Within Rx_mpdu_desc_info_details: 543 544 Mpdu_Sequence_number 545 546 BAR_frame 547 548 Peer_meta_data 549 550 All other fields shall be set to 0 551 552 553 554 <legal all> 555 */ 556 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 557 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 558 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 559 560 /* Description REO_ENTRANCE_RING_5_RESERVED_5A 561 562 <legal 0> 563 */ 564 #define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 565 #define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 566 #define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 567 568 /* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON 569 570 Indicates why rxdma pushed the frame to this ring 571 572 573 574 This field is ignored by REO. 575 576 577 578 <enum 0 rxdma_error_detected> RXDMA detected an error an 579 pushed this frame to this queue 580 581 <enum 1 rxdma_routing_instruction> RXDMA pushed the 582 frame to this queue per received routing instructions. No 583 error within RXDMA was detected 584 585 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 586 result the MSDU link descriptor might not have the 587 last_msdu_in_mpdu_flag set, but instead WBM might just see a 588 NULL pointer in the MSDU link descriptor. This is to be 589 considered a normal condition for this scenario. 590 591 592 593 <legal 0 - 2> 594 */ 595 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 596 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 597 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 598 599 /* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE 600 601 Field only valid when 'rxdma_push_reason' set to 602 'rxdma_error_detected'. 603 604 605 606 This field is ignored by REO. 607 608 609 610 <enum 0 rxdma_overflow_err>MPDU frame is not complete 611 due to a FIFO overflow error in RXPCU. 612 613 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 614 due to receiving incomplete MPDU from the PHY 615 616 617 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 618 error or CRYPTO received an encrypted frame, but did not get 619 a valid corresponding key id in the peer entry. 620 621 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 622 error 623 624 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 625 unencrypted frame error when encrypted was expected 626 627 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 628 length error 629 630 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 631 number of MSDUs allowed in an MPDU got exceeded 632 633 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 634 error 635 636 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 637 parsing error 638 639 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 640 during SA search 641 642 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 643 during DA search 644 645 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 646 timeout during flow search 647 648 <enum 13 Rxdma_flush_request>RXDMA received a flush 649 request 650 */ 651 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 652 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 653 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c 654 655 /* Description REO_ENTRANCE_RING_6_RESERVED_6A 656 657 <legal 0> 658 */ 659 #define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 660 #define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 7 661 #define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xffffff80 662 663 /* Description REO_ENTRANCE_RING_7_RESERVED_7A 664 665 <legal 0> 666 */ 667 #define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c 668 #define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 0 669 #define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000fffff 670 671 /* Description REO_ENTRANCE_RING_7_RING_ID 672 673 Consumer: SW/REO/DEBUG 674 675 Producer: SRNG (of RXDMA) 676 677 678 679 For debugging. 680 681 This field is filled in by the SRNG module. 682 683 It help to identify the ring that is being looked <legal 684 all> 685 */ 686 #define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c 687 #define REO_ENTRANCE_RING_7_RING_ID_LSB 20 688 #define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 689 690 /* Description REO_ENTRANCE_RING_7_LOOPING_COUNT 691 692 Consumer: SW/REO/DEBUG 693 694 Producer: SRNG (of RXDMA) 695 696 697 698 For debugging. 699 700 This field is filled in by the SRNG module. 701 702 703 704 A count value that indicates the number of times the 705 producer of entries into this Ring has looped around the 706 ring. 707 708 At initialization time, this value is set to 0. On the 709 first loop, this value is set to 1. After the max value is 710 reached allowed by the number of bits for this field, the 711 count value continues with 0 again. 712 713 714 715 In case SW is the consumer of the ring entries, it can 716 use this field to figure out up to where the producer of 717 entries has created new entries. This eliminates the need to 718 check where the head pointer' of the ring is located once 719 the SW starts processing an interrupt indicating that new 720 entries have been put into this ring... 721 722 723 724 Also note that SW if it wants only needs to look at the 725 LSB bit of this count value. 726 727 <legal all> 728 */ 729 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 730 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 731 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 732 733 734 #endif // _REO_ENTRANCE_RING_H_ 735