1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _RX_REO_QUEUE_H_ 20 #define _RX_REO_QUEUE_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "uniform_descriptor_header.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0 struct uniform_descriptor_header descriptor_header; 30 // 1 receive_queue_number[15:0], reserved_1b[31:16] 31 // 2 vld[0], associated_link_descriptor_counter[2:1], disable_duplicate_detection[3], soft_reorder_enable[4], ac[6:5], bar[7], rty[8], chk_2k_mode[9], oor_mode[10], ba_window_size[18:11], pn_check_needed[19], pn_shall_be_even[20], pn_shall_be_uneven[21], pn_handling_enable[22], pn_size[24:23], ignore_ampdu_flag[25], reserved_2b[31:26] 32 // 3 svld[0], ssn[12:1], current_index[20:13], seq_2k_error_detected_flag[21], pn_error_detected_flag[22], reserved_3a[30:23], pn_valid[31] 33 // 4 pn_31_0[31:0] 34 // 5 pn_63_32[31:0] 35 // 6 pn_95_64[31:0] 36 // 7 pn_127_96[31:0] 37 // 8 last_rx_enqueue_timestamp[31:0] 38 // 9 last_rx_dequeue_timestamp[31:0] 39 // 10 ptr_to_next_aging_queue_31_0[31:0] 40 // 11 ptr_to_next_aging_queue_39_32[7:0], reserved_11a[31:8] 41 // 12 ptr_to_previous_aging_queue_31_0[31:0] 42 // 13 ptr_to_previous_aging_queue_39_32[7:0], reserved_13a[31:8] 43 // 14 rx_bitmap_31_0[31:0] 44 // 15 rx_bitmap_63_32[31:0] 45 // 16 rx_bitmap_95_64[31:0] 46 // 17 rx_bitmap_127_96[31:0] 47 // 18 rx_bitmap_159_128[31:0] 48 // 19 rx_bitmap_191_160[31:0] 49 // 20 rx_bitmap_223_192[31:0] 50 // 21 rx_bitmap_255_224[31:0] 51 // 22 current_mpdu_count[6:0], current_msdu_count[31:7] 52 // 23 reserved_23[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16] 53 // 24 frames_in_order_count[23:0], bar_received_count[31:24] 54 // 25 mpdu_frames_processed_count[31:0] 55 // 26 msdu_frames_processed_count[31:0] 56 // 27 total_processed_byte_count[31:0] 57 // 28 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16] 58 // 29 reserved_29[31:0] 59 // 30 reserved_30[31:0] 60 // 31 reserved_31[31:0] 61 // 62 // ################ END SUMMARY ################# 63 64 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 65 66 struct rx_reo_queue { 67 struct uniform_descriptor_header descriptor_header; 68 uint32_t receive_queue_number : 16, //[15:0] 69 reserved_1b : 16; //[31:16] 70 uint32_t vld : 1, //[0] 71 associated_link_descriptor_counter: 2, //[2:1] 72 disable_duplicate_detection : 1, //[3] 73 soft_reorder_enable : 1, //[4] 74 ac : 2, //[6:5] 75 bar : 1, //[7] 76 rty : 1, //[8] 77 chk_2k_mode : 1, //[9] 78 oor_mode : 1, //[10] 79 ba_window_size : 8, //[18:11] 80 pn_check_needed : 1, //[19] 81 pn_shall_be_even : 1, //[20] 82 pn_shall_be_uneven : 1, //[21] 83 pn_handling_enable : 1, //[22] 84 pn_size : 2, //[24:23] 85 ignore_ampdu_flag : 1, //[25] 86 reserved_2b : 6; //[31:26] 87 uint32_t svld : 1, //[0] 88 ssn : 12, //[12:1] 89 current_index : 8, //[20:13] 90 seq_2k_error_detected_flag : 1, //[21] 91 pn_error_detected_flag : 1, //[22] 92 reserved_3a : 8, //[30:23] 93 pn_valid : 1; //[31] 94 uint32_t pn_31_0 : 32; //[31:0] 95 uint32_t pn_63_32 : 32; //[31:0] 96 uint32_t pn_95_64 : 32; //[31:0] 97 uint32_t pn_127_96 : 32; //[31:0] 98 uint32_t last_rx_enqueue_timestamp : 32; //[31:0] 99 uint32_t last_rx_dequeue_timestamp : 32; //[31:0] 100 uint32_t ptr_to_next_aging_queue_31_0 : 32; //[31:0] 101 uint32_t ptr_to_next_aging_queue_39_32 : 8, //[7:0] 102 reserved_11a : 24; //[31:8] 103 uint32_t ptr_to_previous_aging_queue_31_0: 32; //[31:0] 104 uint32_t ptr_to_previous_aging_queue_39_32: 8, //[7:0] 105 reserved_13a : 24; //[31:8] 106 uint32_t rx_bitmap_31_0 : 32; //[31:0] 107 uint32_t rx_bitmap_63_32 : 32; //[31:0] 108 uint32_t rx_bitmap_95_64 : 32; //[31:0] 109 uint32_t rx_bitmap_127_96 : 32; //[31:0] 110 uint32_t rx_bitmap_159_128 : 32; //[31:0] 111 uint32_t rx_bitmap_191_160 : 32; //[31:0] 112 uint32_t rx_bitmap_223_192 : 32; //[31:0] 113 uint32_t rx_bitmap_255_224 : 32; //[31:0] 114 uint32_t current_mpdu_count : 7, //[6:0] 115 current_msdu_count : 25; //[31:7] 116 uint32_t reserved_23 : 4, //[3:0] 117 timeout_count : 6, //[9:4] 118 forward_due_to_bar_count : 6, //[15:10] 119 duplicate_count : 16; //[31:16] 120 uint32_t frames_in_order_count : 24, //[23:0] 121 bar_received_count : 8; //[31:24] 122 uint32_t mpdu_frames_processed_count : 32; //[31:0] 123 uint32_t msdu_frames_processed_count : 32; //[31:0] 124 uint32_t total_processed_byte_count : 32; //[31:0] 125 uint32_t late_receive_mpdu_count : 12, //[11:0] 126 window_jump_2k : 4, //[15:12] 127 hole_count : 16; //[31:16] 128 uint32_t reserved_29 : 32; //[31:0] 129 uint32_t reserved_30 : 32; //[31:0] 130 uint32_t reserved_31 : 32; //[31:0] 131 }; 132 133 /* 134 135 struct uniform_descriptor_header descriptor_header 136 137 Details about which module owns this struct. 138 139 Note that sub field Buffer_type shall be set to 140 Receive_REO_queue_descriptor 141 142 receive_queue_number 143 144 Indicates the MPDU queue ID to which this MPDU link 145 descriptor belongs 146 147 Used for tracking and debugging 148 149 <legal all> 150 151 reserved_1b 152 153 <legal 0> 154 155 vld 156 157 Valid bit indicating a session is established and the 158 queue descriptor is valid(Filled by SW) 159 160 <legal all> 161 162 associated_link_descriptor_counter 163 164 Indicates which of the 3 link descriptor counters shall 165 be incremented or decremented when link descriptors are 166 added or removed from this flow queue. 167 168 MSDU link descriptors related with MPDUs stored in the 169 re-order buffer shall also be included in this count. 170 171 172 173 <legal 0-2> 174 175 disable_duplicate_detection 176 177 When set, do not perform any duplicate detection. 178 179 180 181 <legal all> 182 183 soft_reorder_enable 184 185 When set, REO has been instructed to not perform the 186 actual re-ordering of frames for this queue, but just to 187 insert the reorder opcodes. 188 189 190 191 Note that this implies that REO is also not going to 192 perform any MSDU level operations, and the entire MPDU (and 193 thus pointer to the MSDU link descriptor) will be pushed to 194 a destination ring that SW has programmed in a SW 195 programmable configuration register in REO 196 197 198 199 <legal all> 200 201 ac 202 203 Indicates which access category the queue descriptor 204 belongs to(filled by SW) 205 206 <legal all> 207 208 bar 209 210 Indicates if BAR has been received (mostly used for 211 debug purpose and this is filled by REO) 212 213 <legal all> 214 215 rty 216 217 Retry bit is checked if this bit is set. 218 219 <legal all> 220 221 chk_2k_mode 222 223 Indicates what type of operation is expected from Reo 224 when the received frame SN falls within the 2K window 225 226 227 228 See REO MLD document for programming details. 229 230 <legal all> 231 232 oor_mode 233 234 Out of Order mode: 235 236 Indicates what type of operation is expected when the 237 received frame falls within the OOR window. 238 239 240 241 See REO MLD document for programming details. 242 243 <legal all> 244 245 ba_window_size 246 247 Indicates the negotiated (window size + 1). 248 249 it can go up to Max of 256bits. 250 251 252 253 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 254 (means non-BA session, with window size of 0). The 3 values 255 here are the main values validated, but other values should 256 work as well. 257 258 259 260 A BA window size of 0 (=> one frame entry bitmat), means 261 that there is NO RX_REO_QUEUE_EXT descriptor following this 262 RX_REO_QUEUE STRUCT in memory 263 264 265 266 A BA window size of 1 - 105, means that there is 1 267 RX_REO_QUEUE_EXT descriptor directly following this 268 RX_REO_QUEUE STRUCT in memory. 269 270 271 272 A BA window size of 106 - 210, means that there are 2 273 RX_REO_QUEUE_EXT descriptors directly following this 274 RX_REO_QUEUE STRUCT in memory 275 276 277 278 A BA window size of 211 - 256, means that there are 3 279 RX_REO_QUEUE_EXT descriptors directly following this 280 RX_REO_QUEUE STRUCT in memory 281 282 283 284 <legal 0 - 255> 285 286 pn_check_needed 287 288 When set, REO shall perform the PN increment check 289 290 <legal all> 291 292 pn_shall_be_even 293 294 Field only valid when 'pn_check_needed' is set. 295 296 297 298 When set, REO shall confirm that the received PN number 299 is not only incremented, but also always an even number 300 301 <legal all> 302 303 pn_shall_be_uneven 304 305 Field only valid when 'pn_check_needed' is set. 306 307 308 309 When set, REO shall confirm that the received PN number 310 is not only incremented, but also always an uneven number 311 312 <legal all> 313 314 pn_handling_enable 315 316 Field only valid when 'pn_check_needed' is set. 317 318 319 320 When set, and REO detected a PN error, HW shall set the 321 'pn_error_detected_flag'. 322 323 <legal all> 324 325 pn_size 326 327 Size of the PN field check. 328 329 Needed for wrap around handling... 330 331 332 333 <enum 0 pn_size_24> 334 335 <enum 1 pn_size_48> 336 337 <enum 2 pn_size_128> 338 339 340 341 <legal 0-2> 342 343 ignore_ampdu_flag 344 345 When set, REO shall ignore the ampdu_flag on the 346 entrance descriptor for this queue. 347 348 <legal all> 349 350 reserved_2b 351 352 <legal 0> 353 354 svld 355 356 Sequence number in next field is valid one. It can be 357 filled by SW if the want to fill in the any negotiated SSN, 358 otherwise REO will fill the sequence number of first 359 received packet and set this bit to 1. 360 361 <legal all> 362 363 ssn 364 365 Starting Sequence number of the session, this changes 366 whenever window moves. (can be filled by SW then maintained 367 by REO) 368 369 <legal all> 370 371 current_index 372 373 Points to last forwarded packet 374 375 <legal all> 376 377 seq_2k_error_detected_flag 378 379 Set by REO, can only be cleared by SW 380 381 382 383 When set, REO has detected a 2k error jump in the 384 sequence number and from that moment forward, all new frames 385 are forwarded directly to FW, without duplicate detect, 386 reordering, etc. 387 388 <legal all> 389 390 pn_error_detected_flag 391 392 Set by REO, can only be cleared by SW 393 394 395 396 When set, REO has detected a PN error and from that 397 moment forward, all new frames are forwarded directly to FW, 398 without duplicate detect, reordering, etc. 399 400 <legal all> 401 402 reserved_3a 403 404 <legal 0> 405 406 pn_valid 407 408 PN number in next fields are valid. It can be filled by 409 SW if it wants to fill in the any negotiated SSN, otherwise 410 REO will fill the pn based on the first received packet and 411 set this bit to 1. 412 413 <legal all> 414 415 pn_31_0 416 417 418 <legal all> 419 420 pn_63_32 421 422 Bits [63:32] of the PN number. 423 424 <legal all> 425 426 pn_95_64 427 428 Bits [95:64] of the PN number. 429 430 <legal all> 431 432 pn_127_96 433 434 Bits [127:96] of the PN number. 435 436 <legal all> 437 438 last_rx_enqueue_timestamp 439 440 This timestamp is updated when an MPDU is received and 441 accesses this Queue Descriptor. It does not include the 442 access due to Command TLVs or Aging (which will be updated 443 in Last_rx_dequeue_timestamp). 444 445 <legal all> 446 447 last_rx_dequeue_timestamp 448 449 This timestamp is used for Aging. When an MPDU or 450 multiple MPDUs are forwarded, either due to window movement, 451 bar, aging or command flush, this timestamp is updated. Also 452 when the bitmap is all zero and the first time an MPDU is 453 queued (opcode=QCUR), this timestamp is updated for aging. 454 455 <legal all> 456 457 ptr_to_next_aging_queue_31_0 458 459 Address (address bits 31-0)of next RX_REO_QUEUE 460 descriptor in the 'receive timestamp' ordered list. 461 462 From it the Position of this queue descriptor in the per 463 AC aging waitlist can be derived. 464 465 Value 0x0 indicates the 'NULL' pointer which implies 466 that this is the last entry in the list. 467 468 <legal all> 469 470 ptr_to_next_aging_queue_39_32 471 472 Address (address bits 39-32)of next RX_REO_QUEUE 473 descriptor in the 'receive timestamp' ordered list. 474 475 From it the Position of this queue descriptor in the per 476 AC aging waitlist can be derived. 477 478 Value 0x0 indicates the 'NULL' pointer which implies 479 that this is the last entry in the list. 480 481 <legal all> 482 483 reserved_11a 484 485 <legal 0> 486 487 ptr_to_previous_aging_queue_31_0 488 489 Address (address bits 31-0)of next RX_REO_QUEUE 490 descriptor in the 'receive timestamp' ordered list. 491 492 From it the Position of this queue descriptor in the per 493 AC aging waitlist can be derived. 494 495 Value 0x0 indicates the 'NULL' pointer which implies 496 that this is the first entry in the list. 497 498 <legal all> 499 500 ptr_to_previous_aging_queue_39_32 501 502 Address (address bits 39-32)of next RX_REO_QUEUE 503 descriptor in the 'receive timestamp' ordered list. 504 505 From it the Position of this queue descriptor in the per 506 AC aging waitlist can be derived. 507 508 Value 0x0 indicates the 'NULL' pointer which implies 509 that this is the first entry in the list. 510 511 <legal all> 512 513 reserved_13a 514 515 <legal 0> 516 517 rx_bitmap_31_0 518 519 When a bit is set, the corresponding frame is currently 520 held in the re-order queue. 521 522 The bitmap is Fully managed by HW. 523 524 SW shall init this to 0, and then never ever change it 525 526 <legal all> 527 528 rx_bitmap_63_32 529 530 See Rx_bitmap_31_0 description 531 532 <legal all> 533 534 rx_bitmap_95_64 535 536 See Rx_bitmap_31_0 description 537 538 <legal all> 539 540 rx_bitmap_127_96 541 542 See Rx_bitmap_31_0 description 543 544 <legal all> 545 546 rx_bitmap_159_128 547 548 See Rx_bitmap_31_0 description 549 550 <legal all> 551 552 rx_bitmap_191_160 553 554 See Rx_bitmap_31_0 description 555 556 <legal all> 557 558 rx_bitmap_223_192 559 560 See Rx_bitmap_31_0 description 561 562 <legal all> 563 564 rx_bitmap_255_224 565 566 See Rx_bitmap_31_0 description 567 568 <legal all> 569 570 current_mpdu_count 571 572 The number of MPDUs in the queue. 573 574 575 576 <legal all> 577 578 current_msdu_count 579 580 The number of MSDUs in the queue. 581 582 <legal all> 583 584 reserved_23 585 586 <legal 0> 587 588 timeout_count 589 590 The number of times that REO started forwarding frames 591 even though there is a hole in the bitmap. Forwarding reason 592 is Timeout 593 594 595 596 The counter saturates and freezes at 0x3F 597 598 599 600 <legal all> 601 602 forward_due_to_bar_count 603 604 The number of times that REO started forwarding frames 605 even though there is a hole in the bitmap. Forwarding reason 606 is reception of BAR frame. 607 608 609 610 The counter saturates and freezes at 0x3F 611 612 613 614 <legal all> 615 616 duplicate_count 617 618 The number of duplicate frames that have been detected 619 620 <legal all> 621 622 frames_in_order_count 623 624 The number of frames that have been received in order 625 (without a hole that prevented them from being forwarded 626 immediately) 627 628 629 630 This corresponds to the Reorder opcodes: 631 632 'FWDCUR' and 'FWD BUF' 633 634 635 636 <legal all> 637 638 bar_received_count 639 640 The number of times a BAR frame is received. 641 642 643 644 This corresponds to the Reorder opcodes with 'DROP' 645 646 647 648 The counter saturates and freezes at 0xFF 649 650 <legal all> 651 652 mpdu_frames_processed_count 653 654 The total number of MPDU frames that have been processed 655 by REO. 'Processing' here means that REO has received them 656 out of the entrance ring, and retrieved the corresponding 657 RX_REO_QUEUE Descriptor. 658 659 660 661 Note that this count includes duplicates, frames that 662 later had errors, etc. 663 664 665 666 Note that field 'Duplicate_count' indicates how many of 667 these MPDUs were duplicates. 668 669 670 671 <legal all> 672 673 msdu_frames_processed_count 674 675 The total number of MSDU frames that have been processed 676 by REO. 'Processing' here means that REO has received them 677 out of the entrance ring, and retrieved the corresponding 678 RX_REO_QUEUE Descriptor. 679 680 681 682 Note that this count includes duplicates, frames that 683 later had errors, etc. 684 685 686 687 <legal all> 688 689 total_processed_byte_count 690 691 An approximation of the number of bytes processed for 692 this queue. 693 694 'Processing' here means that REO has received them out 695 of the entrance ring, and retrieved the corresponding 696 RX_REO_QUEUE Descriptor. 697 698 699 700 Note that this count includes duplicates, frames that 701 later had errors, etc. 702 703 704 705 In 64 byte units 706 707 <legal all> 708 709 late_receive_mpdu_count 710 711 The number of MPDUs received after the window had 712 already moved on. The 'late' sequence window is defined as 713 (Window SSN - 256) - (Window SSN - 1) 714 715 716 717 This corresponds with Out of order detection in 718 duplicate detect FSM 719 720 721 722 The counter saturates and freezes at 0xFFF 723 724 725 726 <legal all> 727 728 window_jump_2k 729 730 The number of times the window moved more then 2K 731 732 733 734 The counter saturates and freezes at 0xF 735 736 737 738 (Note: field name can not start with number: previous 739 2k_window_jump) 740 741 742 743 <legal all> 744 745 hole_count 746 747 The number of times a hole was created in the receive 748 bitmap. 749 750 751 752 This corresponds to the Reorder opcodes with 'QCUR' 753 754 755 756 <legal all> 757 758 reserved_29 759 760 <legal 0> 761 762 reserved_30 763 764 <legal 0> 765 766 reserved_31 767 768 <legal 0> 769 */ 770 771 #define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000 772 #define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0 773 #define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff 774 775 /* Description RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER 776 777 Indicates the MPDU queue ID to which this MPDU link 778 descriptor belongs 779 780 Used for tracking and debugging 781 782 <legal all> 783 */ 784 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 785 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 786 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 787 788 /* Description RX_REO_QUEUE_1_RESERVED_1B 789 790 <legal 0> 791 */ 792 #define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 793 #define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 794 #define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 795 796 /* Description RX_REO_QUEUE_2_VLD 797 798 Valid bit indicating a session is established and the 799 queue descriptor is valid(Filled by SW) 800 801 <legal all> 802 */ 803 #define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 804 #define RX_REO_QUEUE_2_VLD_LSB 0 805 #define RX_REO_QUEUE_2_VLD_MASK 0x00000001 806 807 /* Description RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER 808 809 Indicates which of the 3 link descriptor counters shall 810 be incremented or decremented when link descriptors are 811 added or removed from this flow queue. 812 813 MSDU link descriptors related with MPDUs stored in the 814 re-order buffer shall also be included in this count. 815 816 817 818 <legal 0-2> 819 */ 820 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 821 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 822 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 823 824 /* Description RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION 825 826 When set, do not perform any duplicate detection. 827 828 829 830 <legal all> 831 */ 832 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 833 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 834 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 835 836 /* Description RX_REO_QUEUE_2_SOFT_REORDER_ENABLE 837 838 When set, REO has been instructed to not perform the 839 actual re-ordering of frames for this queue, but just to 840 insert the reorder opcodes. 841 842 843 844 Note that this implies that REO is also not going to 845 perform any MSDU level operations, and the entire MPDU (and 846 thus pointer to the MSDU link descriptor) will be pushed to 847 a destination ring that SW has programmed in a SW 848 programmable configuration register in REO 849 850 851 852 <legal all> 853 */ 854 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 855 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 856 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 857 858 /* Description RX_REO_QUEUE_2_AC 859 860 Indicates which access category the queue descriptor 861 belongs to(filled by SW) 862 863 <legal all> 864 */ 865 #define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 866 #define RX_REO_QUEUE_2_AC_LSB 5 867 #define RX_REO_QUEUE_2_AC_MASK 0x00000060 868 869 /* Description RX_REO_QUEUE_2_BAR 870 871 Indicates if BAR has been received (mostly used for 872 debug purpose and this is filled by REO) 873 874 <legal all> 875 */ 876 #define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 877 #define RX_REO_QUEUE_2_BAR_LSB 7 878 #define RX_REO_QUEUE_2_BAR_MASK 0x00000080 879 880 /* Description RX_REO_QUEUE_2_RTY 881 882 Retry bit is checked if this bit is set. 883 884 <legal all> 885 */ 886 #define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 887 #define RX_REO_QUEUE_2_RTY_LSB 8 888 #define RX_REO_QUEUE_2_RTY_MASK 0x00000100 889 890 /* Description RX_REO_QUEUE_2_CHK_2K_MODE 891 892 Indicates what type of operation is expected from Reo 893 when the received frame SN falls within the 2K window 894 895 896 897 See REO MLD document for programming details. 898 899 <legal all> 900 */ 901 #define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 902 #define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 903 #define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 904 905 /* Description RX_REO_QUEUE_2_OOR_MODE 906 907 Out of Order mode: 908 909 Indicates what type of operation is expected when the 910 received frame falls within the OOR window. 911 912 913 914 See REO MLD document for programming details. 915 916 <legal all> 917 */ 918 #define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 919 #define RX_REO_QUEUE_2_OOR_MODE_LSB 10 920 #define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 921 922 /* Description RX_REO_QUEUE_2_BA_WINDOW_SIZE 923 924 Indicates the negotiated (window size + 1). 925 926 it can go up to Max of 256bits. 927 928 929 930 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 931 (means non-BA session, with window size of 0). The 3 values 932 here are the main values validated, but other values should 933 work as well. 934 935 936 937 A BA window size of 0 (=> one frame entry bitmat), means 938 that there is NO RX_REO_QUEUE_EXT descriptor following this 939 RX_REO_QUEUE STRUCT in memory 940 941 942 943 A BA window size of 1 - 105, means that there is 1 944 RX_REO_QUEUE_EXT descriptor directly following this 945 RX_REO_QUEUE STRUCT in memory. 946 947 948 949 A BA window size of 106 - 210, means that there are 2 950 RX_REO_QUEUE_EXT descriptors directly following this 951 RX_REO_QUEUE STRUCT in memory 952 953 954 955 A BA window size of 211 - 256, means that there are 3 956 RX_REO_QUEUE_EXT descriptors directly following this 957 RX_REO_QUEUE STRUCT in memory 958 959 960 961 <legal 0 - 255> 962 */ 963 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 964 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 965 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 966 967 /* Description RX_REO_QUEUE_2_PN_CHECK_NEEDED 968 969 When set, REO shall perform the PN increment check 970 971 <legal all> 972 */ 973 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 974 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 975 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 976 977 /* Description RX_REO_QUEUE_2_PN_SHALL_BE_EVEN 978 979 Field only valid when 'pn_check_needed' is set. 980 981 982 983 When set, REO shall confirm that the received PN number 984 is not only incremented, but also always an even number 985 986 <legal all> 987 */ 988 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 989 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 990 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 991 992 /* Description RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN 993 994 Field only valid when 'pn_check_needed' is set. 995 996 997 998 When set, REO shall confirm that the received PN number 999 is not only incremented, but also always an uneven number 1000 1001 <legal all> 1002 */ 1003 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 1004 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 1005 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 1006 1007 /* Description RX_REO_QUEUE_2_PN_HANDLING_ENABLE 1008 1009 Field only valid when 'pn_check_needed' is set. 1010 1011 1012 1013 When set, and REO detected a PN error, HW shall set the 1014 'pn_error_detected_flag'. 1015 1016 <legal all> 1017 */ 1018 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 1019 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 1020 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 1021 1022 /* Description RX_REO_QUEUE_2_PN_SIZE 1023 1024 Size of the PN field check. 1025 1026 Needed for wrap around handling... 1027 1028 1029 1030 <enum 0 pn_size_24> 1031 1032 <enum 1 pn_size_48> 1033 1034 <enum 2 pn_size_128> 1035 1036 1037 1038 <legal 0-2> 1039 */ 1040 #define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 1041 #define RX_REO_QUEUE_2_PN_SIZE_LSB 23 1042 #define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 1043 1044 /* Description RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG 1045 1046 When set, REO shall ignore the ampdu_flag on the 1047 entrance descriptor for this queue. 1048 1049 <legal all> 1050 */ 1051 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 1052 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 1053 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 1054 1055 /* Description RX_REO_QUEUE_2_RESERVED_2B 1056 1057 <legal 0> 1058 */ 1059 #define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 1060 #define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 1061 #define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 1062 1063 /* Description RX_REO_QUEUE_3_SVLD 1064 1065 Sequence number in next field is valid one. It can be 1066 filled by SW if the want to fill in the any negotiated SSN, 1067 otherwise REO will fill the sequence number of first 1068 received packet and set this bit to 1. 1069 1070 <legal all> 1071 */ 1072 #define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c 1073 #define RX_REO_QUEUE_3_SVLD_LSB 0 1074 #define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 1075 1076 /* Description RX_REO_QUEUE_3_SSN 1077 1078 Starting Sequence number of the session, this changes 1079 whenever window moves. (can be filled by SW then maintained 1080 by REO) 1081 1082 <legal all> 1083 */ 1084 #define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c 1085 #define RX_REO_QUEUE_3_SSN_LSB 1 1086 #define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe 1087 1088 /* Description RX_REO_QUEUE_3_CURRENT_INDEX 1089 1090 Points to last forwarded packet 1091 1092 <legal all> 1093 */ 1094 #define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c 1095 #define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 1096 #define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 1097 1098 /* Description RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG 1099 1100 Set by REO, can only be cleared by SW 1101 1102 1103 1104 When set, REO has detected a 2k error jump in the 1105 sequence number and from that moment forward, all new frames 1106 are forwarded directly to FW, without duplicate detect, 1107 reordering, etc. 1108 1109 <legal all> 1110 */ 1111 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 1112 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 1113 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 1114 1115 /* Description RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG 1116 1117 Set by REO, can only be cleared by SW 1118 1119 1120 1121 When set, REO has detected a PN error and from that 1122 moment forward, all new frames are forwarded directly to FW, 1123 without duplicate detect, reordering, etc. 1124 1125 <legal all> 1126 */ 1127 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 1128 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 1129 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 1130 1131 /* Description RX_REO_QUEUE_3_RESERVED_3A 1132 1133 <legal 0> 1134 */ 1135 #define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c 1136 #define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 1137 #define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 1138 1139 /* Description RX_REO_QUEUE_3_PN_VALID 1140 1141 PN number in next fields are valid. It can be filled by 1142 SW if it wants to fill in the any negotiated SSN, otherwise 1143 REO will fill the pn based on the first received packet and 1144 set this bit to 1. 1145 1146 <legal all> 1147 */ 1148 #define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c 1149 #define RX_REO_QUEUE_3_PN_VALID_LSB 31 1150 #define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 1151 1152 /* Description RX_REO_QUEUE_4_PN_31_0 1153 1154 1155 <legal all> 1156 */ 1157 #define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 1158 #define RX_REO_QUEUE_4_PN_31_0_LSB 0 1159 #define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff 1160 1161 /* Description RX_REO_QUEUE_5_PN_63_32 1162 1163 Bits [63:32] of the PN number. 1164 1165 <legal all> 1166 */ 1167 #define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 1168 #define RX_REO_QUEUE_5_PN_63_32_LSB 0 1169 #define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff 1170 1171 /* Description RX_REO_QUEUE_6_PN_95_64 1172 1173 Bits [95:64] of the PN number. 1174 1175 <legal all> 1176 */ 1177 #define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 1178 #define RX_REO_QUEUE_6_PN_95_64_LSB 0 1179 #define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff 1180 1181 /* Description RX_REO_QUEUE_7_PN_127_96 1182 1183 Bits [127:96] of the PN number. 1184 1185 <legal all> 1186 */ 1187 #define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c 1188 #define RX_REO_QUEUE_7_PN_127_96_LSB 0 1189 #define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff 1190 1191 /* Description RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP 1192 1193 This timestamp is updated when an MPDU is received and 1194 accesses this Queue Descriptor. It does not include the 1195 access due to Command TLVs or Aging (which will be updated 1196 in Last_rx_dequeue_timestamp). 1197 1198 <legal all> 1199 */ 1200 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 1201 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 1202 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 1203 1204 /* Description RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP 1205 1206 This timestamp is used for Aging. When an MPDU or 1207 multiple MPDUs are forwarded, either due to window movement, 1208 bar, aging or command flush, this timestamp is updated. Also 1209 when the bitmap is all zero and the first time an MPDU is 1210 queued (opcode=QCUR), this timestamp is updated for aging. 1211 1212 <legal all> 1213 */ 1214 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 1215 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 1216 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 1217 1218 /* Description RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0 1219 1220 Address (address bits 31-0)of next RX_REO_QUEUE 1221 descriptor in the 'receive timestamp' ordered list. 1222 1223 From it the Position of this queue descriptor in the per 1224 AC aging waitlist can be derived. 1225 1226 Value 0x0 indicates the 'NULL' pointer which implies 1227 that this is the last entry in the list. 1228 1229 <legal all> 1230 */ 1231 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 1232 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 1233 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 1234 1235 /* Description RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32 1236 1237 Address (address bits 39-32)of next RX_REO_QUEUE 1238 descriptor in the 'receive timestamp' ordered list. 1239 1240 From it the Position of this queue descriptor in the per 1241 AC aging waitlist can be derived. 1242 1243 Value 0x0 indicates the 'NULL' pointer which implies 1244 that this is the last entry in the list. 1245 1246 <legal all> 1247 */ 1248 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 1249 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 1250 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 1251 1252 /* Description RX_REO_QUEUE_11_RESERVED_11A 1253 1254 <legal 0> 1255 */ 1256 #define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c 1257 #define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 1258 #define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 1259 1260 /* Description RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0 1261 1262 Address (address bits 31-0)of next RX_REO_QUEUE 1263 descriptor in the 'receive timestamp' ordered list. 1264 1265 From it the Position of this queue descriptor in the per 1266 AC aging waitlist can be derived. 1267 1268 Value 0x0 indicates the 'NULL' pointer which implies 1269 that this is the first entry in the list. 1270 1271 <legal all> 1272 */ 1273 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 1274 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 1275 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 1276 1277 /* Description RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32 1278 1279 Address (address bits 39-32)of next RX_REO_QUEUE 1280 descriptor in the 'receive timestamp' ordered list. 1281 1282 From it the Position of this queue descriptor in the per 1283 AC aging waitlist can be derived. 1284 1285 Value 0x0 indicates the 'NULL' pointer which implies 1286 that this is the first entry in the list. 1287 1288 <legal all> 1289 */ 1290 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 1291 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 1292 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 1293 1294 /* Description RX_REO_QUEUE_13_RESERVED_13A 1295 1296 <legal 0> 1297 */ 1298 #define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 1299 #define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 1300 #define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 1301 1302 /* Description RX_REO_QUEUE_14_RX_BITMAP_31_0 1303 1304 When a bit is set, the corresponding frame is currently 1305 held in the re-order queue. 1306 1307 The bitmap is Fully managed by HW. 1308 1309 SW shall init this to 0, and then never ever change it 1310 1311 <legal all> 1312 */ 1313 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 1314 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 1315 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff 1316 1317 /* Description RX_REO_QUEUE_15_RX_BITMAP_63_32 1318 1319 See Rx_bitmap_31_0 description 1320 1321 <legal all> 1322 */ 1323 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c 1324 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 1325 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff 1326 1327 /* Description RX_REO_QUEUE_16_RX_BITMAP_95_64 1328 1329 See Rx_bitmap_31_0 description 1330 1331 <legal all> 1332 */ 1333 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 1334 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 1335 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff 1336 1337 /* Description RX_REO_QUEUE_17_RX_BITMAP_127_96 1338 1339 See Rx_bitmap_31_0 description 1340 1341 <legal all> 1342 */ 1343 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 1344 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 1345 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff 1346 1347 /* Description RX_REO_QUEUE_18_RX_BITMAP_159_128 1348 1349 See Rx_bitmap_31_0 description 1350 1351 <legal all> 1352 */ 1353 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 1354 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 1355 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff 1356 1357 /* Description RX_REO_QUEUE_19_RX_BITMAP_191_160 1358 1359 See Rx_bitmap_31_0 description 1360 1361 <legal all> 1362 */ 1363 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c 1364 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 1365 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff 1366 1367 /* Description RX_REO_QUEUE_20_RX_BITMAP_223_192 1368 1369 See Rx_bitmap_31_0 description 1370 1371 <legal all> 1372 */ 1373 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 1374 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 1375 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff 1376 1377 /* Description RX_REO_QUEUE_21_RX_BITMAP_255_224 1378 1379 See Rx_bitmap_31_0 description 1380 1381 <legal all> 1382 */ 1383 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 1384 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 1385 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff 1386 1387 /* Description RX_REO_QUEUE_22_CURRENT_MPDU_COUNT 1388 1389 The number of MPDUs in the queue. 1390 1391 1392 1393 <legal all> 1394 */ 1395 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 1396 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 1397 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f 1398 1399 /* Description RX_REO_QUEUE_22_CURRENT_MSDU_COUNT 1400 1401 The number of MSDUs in the queue. 1402 1403 <legal all> 1404 */ 1405 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 1406 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 1407 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 1408 1409 /* Description RX_REO_QUEUE_23_RESERVED_23 1410 1411 <legal 0> 1412 */ 1413 #define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c 1414 #define RX_REO_QUEUE_23_RESERVED_23_LSB 0 1415 #define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f 1416 1417 /* Description RX_REO_QUEUE_23_TIMEOUT_COUNT 1418 1419 The number of times that REO started forwarding frames 1420 even though there is a hole in the bitmap. Forwarding reason 1421 is Timeout 1422 1423 1424 1425 The counter saturates and freezes at 0x3F 1426 1427 1428 1429 <legal all> 1430 */ 1431 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c 1432 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 1433 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 1434 1435 /* Description RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT 1436 1437 The number of times that REO started forwarding frames 1438 even though there is a hole in the bitmap. Forwarding reason 1439 is reception of BAR frame. 1440 1441 1442 1443 The counter saturates and freezes at 0x3F 1444 1445 1446 1447 <legal all> 1448 */ 1449 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c 1450 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 1451 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 1452 1453 /* Description RX_REO_QUEUE_23_DUPLICATE_COUNT 1454 1455 The number of duplicate frames that have been detected 1456 1457 <legal all> 1458 */ 1459 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c 1460 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 1461 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 1462 1463 /* Description RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT 1464 1465 The number of frames that have been received in order 1466 (without a hole that prevented them from being forwarded 1467 immediately) 1468 1469 1470 1471 This corresponds to the Reorder opcodes: 1472 1473 'FWDCUR' and 'FWD BUF' 1474 1475 1476 1477 <legal all> 1478 */ 1479 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 1480 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 1481 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 1482 1483 /* Description RX_REO_QUEUE_24_BAR_RECEIVED_COUNT 1484 1485 The number of times a BAR frame is received. 1486 1487 1488 1489 This corresponds to the Reorder opcodes with 'DROP' 1490 1491 1492 1493 The counter saturates and freezes at 0xFF 1494 1495 <legal all> 1496 */ 1497 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 1498 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 1499 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 1500 1501 /* Description RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT 1502 1503 The total number of MPDU frames that have been processed 1504 by REO. 'Processing' here means that REO has received them 1505 out of the entrance ring, and retrieved the corresponding 1506 RX_REO_QUEUE Descriptor. 1507 1508 1509 1510 Note that this count includes duplicates, frames that 1511 later had errors, etc. 1512 1513 1514 1515 Note that field 'Duplicate_count' indicates how many of 1516 these MPDUs were duplicates. 1517 1518 1519 1520 <legal all> 1521 */ 1522 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 1523 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 1524 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1525 1526 /* Description RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT 1527 1528 The total number of MSDU frames that have been processed 1529 by REO. 'Processing' here means that REO has received them 1530 out of the entrance ring, and retrieved the corresponding 1531 RX_REO_QUEUE Descriptor. 1532 1533 1534 1535 Note that this count includes duplicates, frames that 1536 later had errors, etc. 1537 1538 1539 1540 <legal all> 1541 */ 1542 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 1543 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 1544 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1545 1546 /* Description RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT 1547 1548 An approximation of the number of bytes processed for 1549 this queue. 1550 1551 'Processing' here means that REO has received them out 1552 of the entrance ring, and retrieved the corresponding 1553 RX_REO_QUEUE Descriptor. 1554 1555 1556 1557 Note that this count includes duplicates, frames that 1558 later had errors, etc. 1559 1560 1561 1562 In 64 byte units 1563 1564 <legal all> 1565 */ 1566 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c 1567 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 1568 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 1569 1570 /* Description RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT 1571 1572 The number of MPDUs received after the window had 1573 already moved on. The 'late' sequence window is defined as 1574 (Window SSN - 256) - (Window SSN - 1) 1575 1576 1577 1578 This corresponds with Out of order detection in 1579 duplicate detect FSM 1580 1581 1582 1583 The counter saturates and freezes at 0xFFF 1584 1585 1586 1587 <legal all> 1588 */ 1589 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 1590 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 1591 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 1592 1593 /* Description RX_REO_QUEUE_28_WINDOW_JUMP_2K 1594 1595 The number of times the window moved more then 2K 1596 1597 1598 1599 The counter saturates and freezes at 0xF 1600 1601 1602 1603 (Note: field name can not start with number: previous 1604 2k_window_jump) 1605 1606 1607 1608 <legal all> 1609 */ 1610 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 1611 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 1612 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 1613 1614 /* Description RX_REO_QUEUE_28_HOLE_COUNT 1615 1616 The number of times a hole was created in the receive 1617 bitmap. 1618 1619 1620 1621 This corresponds to the Reorder opcodes with 'QCUR' 1622 1623 1624 1625 <legal all> 1626 */ 1627 #define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 1628 #define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 1629 #define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 1630 1631 /* Description RX_REO_QUEUE_29_RESERVED_29 1632 1633 <legal 0> 1634 */ 1635 #define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 1636 #define RX_REO_QUEUE_29_RESERVED_29_LSB 0 1637 #define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff 1638 1639 /* Description RX_REO_QUEUE_30_RESERVED_30 1640 1641 <legal 0> 1642 */ 1643 #define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 1644 #define RX_REO_QUEUE_30_RESERVED_30_LSB 0 1645 #define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff 1646 1647 /* Description RX_REO_QUEUE_31_RESERVED_31 1648 1649 <legal 0> 1650 */ 1651 #define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c 1652 #define RX_REO_QUEUE_31_RESERVED_31_LSB 0 1653 #define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff 1654 1655 1656 #endif // _RX_REO_QUEUE_H_ 1657